利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

22 条记录 (耗时 0.015 秒)

    Unified programmable computational memory and configuration network
    11.
    发明授权
    Unified programmable computational memory and configuration network 有权

    公开(公告)号：US11201623B2

    公开(公告)日：2021-12-14

    申请号：US16884038

    申请日：2020-05-26

    申请人： XILINX, INC.

    发明人： Rafael C. Camarota

    IPC分类号： H03K19/177 ,  G06F3/06 ,  G06F7/48 ,  H03K19/1776 ,  H03K19/17736 ,  H03K19/17724 ,  G06F7/483 ,  G06F7/502 ,  H03K19/17756

    摘要： Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.

    Layered boundary interconnect
    12.
    发明授权
    Layered boundary interconnect 有权

    公开(公告)号：US10929331B1

    公开(公告)日：2021-02-23

    申请号：US16388474

    申请日：2019-04-18

    申请人： Xilinx, Inc.

    发明人： Rafael C. Camarota

    IPC分类号： G06F13/42 ,  G06F13/20

    摘要： Examples described herein generally relate to a layered boundary interconnect in an integrated circuit (IC) and methods for operating such IC. In an example, an IC includes a programmable logic region, a plurality of input/output circuits, a plurality of hard block circuits, and a programmable native transmission network. The programmable native transmission network is connected to and between the plurality of input/output circuits and the plurality of hard block circuits. The plurality of hard block circuits is connected to and between the programmable native transmission network and the programmable logic region.

    BOUNDARY LOGIC INTERFACE
    13.
    发明申请
    BOUNDARY LOGIC INTERFACE 审中-公开

    公开(公告)号：US20200274536A1

    公开(公告)日：2020-08-27

    申请号：US16285588

    申请日：2019-02-26

    申请人： Xilinx, Inc.

    发明人： Rafael C. Camarota ,  Ui S. Han ,  Weiguang Lu

    IPC分类号： H03K19/177 ,  G06F17/50

    摘要： Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.

    Standalone interface for stacked silicon interconnect (SSI) technology integration
    14.
    发明授权
    Standalone interface for stacked silicon interconnect (SSI) technology integration 有权

    公开(公告)号：US10784121B2

    公开(公告)日：2020-09-22

    申请号：US15237384

    申请日：2016-08-15

    申请人： Xilinx, Inc.

    发明人： Rafael C. Camarota

    IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L29/06 ,  H01L25/18 ,  H01L23/00

    摘要： Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable IC die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable IC die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable IC die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.

    CONFIGURING PROGRAMMABLE LOGIC REGION VIA PROGRAMMABLE NETWORK
    15.
    发明申请
    CONFIGURING PROGRAMMABLE LOGIC REGION VIA PROGRAMMABLE NETWORK 审中-公开

    公开(公告)号：US20200264901A1

    公开(公告)日：2020-08-20

    申请号：US16276178

    申请日：2019-02-14

    申请人： Xilinx, Inc.

    发明人： Rafael C. Camarota ,  David P. Schultz

    IPC分类号： G06F9/445 ,  G06F13/40

    摘要： Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.

    Unified programmable computational memory and configuration network
    16.
    发明授权
    Unified programmable computational memory and configuration network 有权

    公开(公告)号：US10673440B1

    公开(公告)日：2020-06-02

    申请号：US16539220

    申请日：2019-08-13

    申请人： XILINX, INC.

    发明人： Rafael C. Camarota

    IPC分类号： H03K19/177 ,  G06F3/06 ,  G06F7/48 ,  H03K19/1776 ,  H03K19/17736 ,  H03K19/17724 ,  G06F7/483 ,  G06F7/502 ,  H03K19/17756

    摘要： Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.

    HETEROGENEOUS BALL PATTERN PACKAGE
    18.
    发明申请
    HETEROGENEOUS BALL PATTERN PACKAGE 审中-公开

    公开(公告)号：US20180033753A1

    公开(公告)日：2018-02-01

    申请号：US15225550

    申请日：2016-08-01

    申请人： Xilinx, Inc.

    发明人： Rafael C. Camarota

    IPC分类号： H01L23/00 ,  H01L23/498

    CPC分类号： H01L24/09 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5286 ,  H01L24/17 ,  H01L24/83 ,  H01L2224/0903 ,  H01L2224/0912 ,  H01L2224/1712

    摘要： Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls) of an integrated circuit (IC) package (and the corresponding conductive pads of a circuit board for electrical connection with the IC package) using a plurality of different pitches. One example integrated circuit (IC) package generally includes an integrated circuit die and an arrangement of electrically conductive elements coupled to the integrated circuit die. In at least one region of the arrangement, the conductive elements are disposed with a first pitch in a first dimension of the arrangement and with a second pitch in a second dimension of the arrangement, and the second pitch is different from the first pitch. The pitch of a given region may be based on mechanical, PCB routing, and/or signal integrity considerations.

    Rotated integrated circuit die and chip packages having the same
    19.
    发明授权
    Rotated integrated circuit die and chip packages having the same 有权

    公开(公告)号：US09882562B1

    公开(公告)日：2018-01-30

    申请号：US15371472

    申请日：2016-12-07

    申请人： Xilinx, Inc.

    发明人： Martin L. Voogel ,  Rafael C. Camarota ,  Henri Fraisse

    IPC分类号： H03K19/177 ,  H03K19/00 ,  H01L23/498

    CPC分类号： H03K19/0008 ,  H01L23/49811 ,  H01L23/49838 ,  H03K19/17728 ,  H03K19/17744

    摘要： An integrated circuit (IC) die and integrated circuit (IC) chip packages having such dies are described that leverage the symmetry of the arrangement of micro-bumps to advantageously reduce interposer cost and size requirements. In one example, an integrated circuit (IC) die is provided. The IC die includes a die body, a plurality of programmable tiles disposed in the die body, and a plurality of micro-bumps disposed in the die body. The die body includes a front face connecting a bottom exterior surface and a top exterior surface. A centerline of the die body is perpendicular to the front face and bifurcates the top exterior surface. At least two of the programmable tiles are of a common type. The micro-bumps adjacent the front face and coupled to the common type of programmable tiles have a substantially symmetrical orientation relative to a symmetry axis. The symmetry axis being one of (a) collinear with the centerline of the die body, or (b) parallel to the centerline of the die body.