公开(公告)号：US11075650B1

公开(公告)日：2021-07-27

申请号：US16666599

申请日：2019-10-29

Applicant: Xilinx, Inc.

Inventor： Andrew Dow ,  Richard L. Walke

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/07

Abstract: A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code. The first codeword includes a sequence of data arranged according to an order of columns in a first parity-check matrix associated with the QC LDPC code. A codeword reordering stage generates a reordered codeword by changing the sequence of the data in the first codeword based at least in part on a size of one or more circulant submatrices in the first parity-check matrix. An LDPC decoder generates a decoded codeword by decoding the reordered codeword based on a second parity-check matrix associated with the QC LDPC code. In some implementations, the second parity-check matrix may comprise a plurality of second circulant submatrices of a different size than the first circulant submatrices.

公开(公告)号：US11061673B1

公开(公告)日：2021-07-13

申请号：US15944393

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Baris Ozgul ,  Jan Langer ,  Juan J. Noguera Serra ,  Goran H. K. Bilski ,  Richard L. Walke

IPC: G06F9/30 ,  G06F17/16

Abstract: An example core for data processing engine (DPE) includes a first register file configured to provide a first plurality of output lanes, a processor, coupled to the register file, including: a multiply-accumulate (MAC) circuit, and a first permute circuit coupled between the first register file and the MAC circuit. The first permute circuit is configured to generate a first vector by selecting a first set of output lanes from the first plurality of output lanes, and a second permute circuit coupled between the first register file and the MAC circuit. The second permute circuit is configured to generate a second vector by selecting a second set of output lanes from the first plurality of output lanes.

公开(公告)号：US11016822B1

公开(公告)日：2021-05-25

申请号：US15944578

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H. K. Bilski ,  Juan J. Noguera Serra ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke

IPC: G06F9/50 ,  G06F9/48

Abstract: Examples herein describe techniques for communicating directly between cores in an array of data processing engines. In one embodiment, the array is a 2D array where each of the data processing engines includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the cores. Using the interconnect, however, can add latency when transmitting data between the cores. In the embodiments herein, the array includes core-to-core communication links that directly connect one core in the array to another core. The cores can use these communication links to bypass the interconnect and the memory module to transmit data directly.

公开(公告)号：US10990552B1

公开(公告)日：2021-04-27

申请号：US15944464

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran Hk Bilski ,  Peter McColgan ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F13/40 ,  G06F13/42

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.

公开(公告)号：US11972132B2

公开(公告)日：2024-04-30

申请号：US18145810

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran H K Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Tim Tuan ,  David Clarke

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0683 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/7807

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

公开(公告)号：US11108410B1

公开(公告)日：2021-08-31

申请号：US16112588

申请日：2018-08-24

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Christopher H. Dick ,  Nihat E. Tunali

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/09

Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.

公开(公告)号：US10797727B1

公开(公告)日：2020-10-06

申请号：US16137927

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Andrew Dow ,  Andrew M. Whyte ,  Nihat E. Tunali

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/39

Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository to store parity-check information associated with one or more LDPC codes and an LDPC code configurator to receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and to update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The decoder circuit further includes an LDPC decoder circuitry configurable, based on control signals, to perform LDPC decoding of codewords or LDPC encoding of information using the parity-check information from the LDPC repository.

公开(公告)号：US10673564B1

公开(公告)日：2020-06-02

申请号：US16138414

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Christopher H. Dick ,  William A. Wilkie

IPC: H04L1/00 ,  H03M13/29 ,  H03M13/45 ,  H03M13/11 ,  H04B1/38

Abstract: A modem includes an outer transceiver including a soft decision forward error correction (SD-FEC) circuit, wherein the SD-FEC circuit is hardwired and programmable to perform at least one of encoding or decoding data using a code type selected from a plurality of different code types, and an inner transceiver coupled to the SD-FEC circuit, wherein the inner transceiver is implemented in programmable circuitry.

公开(公告)号：US10484012B1

公开(公告)日：2019-11-19

申请号：US15688628

申请日：2017-08-28

Applicant: Xilinx, Inc.

Inventor： Nihat E. Tunali ,  Richard L. Walke ,  Christopher H. Dick

IPC: H03M13/11

Abstract: A decoder circuit includes an input configured to receive an encoded message generated based on a QC-LDPC code. A first layer process unit is configured to process a first layer of a parity check matrix to generate a plurality of log-likelihood ratio (LLR) values corresponding to a plurality of variable nodes associated with the encoded message respectively. The first layer process unit includes a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values. A layer update unit is configured to generate a first LLR value for a first variable node using first and second row update values for the first variable node. An output is configured to provide a decoded message generated based the plurality of LLR values.

公开(公告)号：US09081634B1

公开(公告)日：2015-07-14

申请号：US13672948

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： James M. Simkins ,  Wayne E. Wennekamp ,  John M. Thendean ,  Adam Elkins ,  Richard L. Walke

IPC: G06F7/57

CPC classification number: G06F7/57 ,  G06F7/4806 ,  G06F7/5443 ,  G06F2207/382 ,  G06F2207/3828

Abstract: An apparatus is disclosed. This apparatus includes a digital signal processing (“DSP”) block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit (“ALU”) block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.

Abstract translation: 公开了一种装置。 该装置包括数字信号处理（“DSP”）块，其具有被耦合以接收第一至第四输入操作数的前置寄存器块。 乘法器耦合到前置寄存器块以接收被乘数的操作数和乘法器操作数。 第一寄存器块耦合到乘法器以从乘法器接收部分乘积的集合。 耦合以接收第三操作数输入的第二寄存器块。 算术逻辑单元（“ALU”）块耦合到预加器寄存器块，第一寄存器块和第二寄存器块。 ALU块包括四个输入多路复用器和一个ALU，其中ALU被耦合以接收四个输入多路复用器中的每一个的输出。