中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.025 seconds)

    Practical approach to layout migration
    11.
    发明授权
    Practical approach to layout migration 有权
    布局迁移的实际方法

    公开(公告)号：US08745554B2

    公开(公告)日：2014-06-03

    申请号：US12647997

    申请日：2009-12-28

    Applicant: Ying-Chou Cheng ,  Tsong-Hua Ou ,  Josh J. H. Feng ,  Cheng-Lung Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    Inventor： Ying-Chou Cheng ,  Tsong-Hua Ou ,  Josh J. H. Feng ,  Cheng-Lung Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.

    Abstract translation: 本公开提供了许多不同实施例中的集成电路设计方法。 一种示例性的IC设计方法包括在第一技术节点中提供电路的IC设计布局; 将电路的IC设计布局迁移到第二个技术节点; 根据电路的电气参数对迁移的IC设计布局进行电气图案化（ePatterning）修改; 然后根据第二技术节点中的电路的迁移的IC设计布局制造掩模。

    Practical Approach to Layout Migration
    16.
    发明申请
    Practical Approach to Layout Migration 有权
    布局迁移的实践方法

    公开(公告)号：US20110161907A1

    公开(公告)日：2011-06-30

    申请号：US12647997

    申请日：2009-12-28

    Applicant: Ying-Chou Cheng ,  Tsong-Hua Ou ,  Josh J.H. Feng ,  Cheng-Lung Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    Inventor： Ying-Chou Cheng ,  Tsong-Hua Ou ,  Josh J.H. Feng ,  Cheng-Lung Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.

    Abstract translation: 本公开提供了许多不同实施例中的集成电路设计方法。 一种示例性的IC设计方法包括在第一技术节点中提供电路的IC设计布局; 将电路的IC设计布局迁移到第二个技术节点; 根据电路的电气参数对迁移的IC设计布局进行电气图案化（ePatterning）修改; 然后根据第二技术节点中的电路的迁移的IC设计布局制造掩模。

    Topography-aware lithography pattern check
    18.
    发明授权
    Topography-aware lithography pattern check 有权
    地形感知光刻图案检查

    公开(公告)号：US09367655B2

    公开(公告)日：2016-06-14

    申请号：US13443568

    申请日：2012-04-10

    Applicant: I-Chang Shih ,  Chung-min Fu ,  Ying-Chou Cheng ,  Yung-Fong Lu ,  Feng-Yuan Chiu ,  Chiu Hsiu Chen

    Inventor： I-Chang Shih ,  Chung-min Fu ,  Ying-Chou Cheng ,  Yung-Fong Lu ,  Feng-Yuan Chiu ,  Chiu Hsiu Chen

    IPC: H01L21/66 ,  G06F17/50 ,  G03F7/20

    CPC classification number: G06F17/5027 ,  G03F7/705 ,  H01L22/10 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.

    Abstract translation: 本公开提供了一种方法。 该方法包括获得集成电路（IC）布局。 该方法包括提供抛光过程模拟模型。 该方法包括对IC布局执行光刻图案校验（LPC）处理。 LPC处理至少部分地使用抛光工艺模拟模型进行。 该方法包括响应于LPC过程检测IC布局上的可能问题区域。 该方法包括修改抛光过程仿真模型。 该方法包括重复执行LPC处理和使用改进的抛光处理模拟模型来检测可能的问题区域。

    Topography-Aware Lithography Pattern Check
    19.
    发明申请
    Topography-Aware Lithography Pattern Check 有权
    地形感知光刻图案检查

    公开(公告)号：US20130267047A1

    公开(公告)日：2013-10-10

    申请号：US13443568

    申请日：2012-04-10

    Applicant: I-Chang Shih ,  Chung-min Fu ,  Ying-Chou Cheng ,  Yung-Fong Lu ,  Feng-Yuan Chiu ,  Chiu Hsiu Chen

    Inventor： I-Chang Shih ,  Chung-min Fu ,  Ying-Chou Cheng ,  Yung-Fong Lu ,  Feng-Yuan Chiu ,  Chiu Hsiu Chen

    IPC: H01L21/66 ,  G06F17/50

    CPC classification number: G06F17/5027 ,  G03F7/705 ,  H01L22/10 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.

    Abstract translation: 本公开提供了一种方法。 该方法包括获得集成电路（IC）布局。 该方法包括提供抛光过程模拟模型。 该方法包括对IC布局执行光刻图案校验（LPC）处理。 LPC处理至少部分地使用抛光工艺模拟模型进行。 该方法包括响应于LPC过程检测IC布局上的可能问题区域。 该方法包括修改抛光过程仿真模型。 该方法包括重复执行LPC处理和使用改进的抛光处理模拟模型来检测可能的问题区域。

    Target-based thermal design using dummy insertion for semiconductor devices
    20.
    发明授权
    Target-based thermal design using dummy insertion for semiconductor devices 有权
    基于目标的热设计，使用半导体器件的虚拟插入

    公开(公告)号：US08527918B2

    公开(公告)日：2013-09-03

    申请号：US13227118

    申请日：2011-09-07

    Applicant: Ying-Chou Cheng ,  Boren Luo ,  Wen-Hao Liu ,  Tsong-Hua Ou ,  Chih-Wei Hsu ,  Wen-Chun Huang ,  Ru-Gun Liu

    Inventor： Ying-Chou Cheng ,  Boren Luo ,  Wen-Hao Liu ,  Tsong-Hua Ou ,  Chih-Wei Hsu ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  G06F2217/80 ,  Y02P90/265

    Abstract: The present disclosure provides integrated circuit methods for target-based dummy insertion. A method includes providing an integrated circuit (IC) design layout, and providing a thermal model for simulating thermal effect on the IC design layout, the thermal model including optical simulation and silicon calibration. The method further includes providing a convolution of the thermal model and the IC design layout to generate a thermal image profile of the IC design layout, defining a thermal target for optimizing thermal uniformity across the thermal image profile, comparing the thermal target and the thermal image profile to determine a difference data, and performing thermal dummy insertion to the IC design layout based on the difference data to provide a target-based IC design layout.

    Abstract translation: 本公开提供了用于基于目标的虚拟插入的集成电路方法。 一种方法包括提供集成电路（IC）设计布局，并提供用于模拟IC设计布局热效应的热模型，热模型包括光学仿真和硅校准。 该方法还包括提供热模型和IC设计布局的卷积以产生IC设计布局的热图像轮廓，定义用于优化热图像轮廓的热均匀性的热目标，比较热目标和热图像 以确定差异数据，并且基于差异数据对IC设计布局进行热假插入以提供基于目标的IC设计布局。

Patent Agency Ranking