Abstract:
An implantable medical device (IMD) includes a sensor for monitoring parameters indicative of sleep disordered breathing. The IMD also includes a position sensor that indicates the relative position and/or activity level of the patient. The position sensor data is used in one or more ways in conjunction with the SDB sensing. The position data is used to confirm that such sensed data is likely indicative of SDB or to select the appropriate criteria for comparison.
Abstract:
Provided is a write circuit of a DDR SDRAM, in which a clock domain crossing is generated from a writing driver during a data write operation and a proper data is always transferred to a gio bus line by using the delay of an internal data strobe signal's falling for a certain amount of time as an input data strobe bar signal. Moreover, by using a skew detection circuit, it is possible to detect a skew tDQSS between a clock and a data strobe, and the skew tDQSS is automatically compensated by the skew compensation circuit. From the perspective of a timing error between the clock and the data strobe, therefore, the write operation of the DDR SDRAM has twice the timing margin (0.5tCK) compared to that of the related art. This means that a stable, high-speed write operation of the DDR SDRAM can be made possible.
Abstract:
The present invention relates to a synthesis of a 7-membered carbocyclic compound having diexomethylene groups, more particularly to a synthesis of a 7-membered carbocyclic compound having diexomethylene groups, a novel compound having the structure represented by the following Chemical Formula 1, from trimethylsilanylmethyl-allenol derivative by the intramolecular Prins cyclization using Lewis acid. The 7-membered carbocyclic compound is a useful intermediate for synthesis of other multicyclic compounds. In Chemical Formula 1, R1 is a C1 to C6 alkyl group, and R2 and R3 is respectively a hydrogen atom, or R1, R2 and R3 may be connected with neighboring substituents to form a 5 to 10-membered aliphatic or aromatic ring.
Abstract:
The present invention provides a system and method for estimating duplicate data in a storage system. A duplicate estimation application executes on a client of a storage system selects an element from an intended destination such as, e.g., a data store of the storage system. If the element is a file (or other data container), the application reads data from the file and computes a fingerprint of the read data. The computed fingerprint is then logged in a fingerprint database, which is illustratively stored on a storage device connected to the client executing the application. This process repeats until the entire file (or other data container) has been read and fingerprinted. Once all elements have been scanned, fingerprinted and recorded, the application identifies any unique entries within the fingerprint database. Utilizing this information, the application computes an estimated space savings that may be realized by employing a data de-duplication technique.
Abstract:
Devices for cleaning and preparing pavement cracks for sealing are disclosed. An example device comprises a wire brush assembly for removal of mid and large-sized debris, an air blaster for removal of fine-grained particulate, a heat lance, and a vacuum for controlled removal of debris and particulates. The example device would also have means for attachment to an air compressor.
Abstract:
Detection of volume depletion, particularly after an incidence of volume overload is disclosed. Various methods, systems, and devices are disclosed that sense and analyze a physiological parameter related to a patient's fluid level in order to warn patients of potentially dangerous volume depletion conditions while minimizing false notifications.
Abstract:
Methods and devices for determining optimal Atrial to Ventricular (AV) pacing intervals and Ventricular to Ventricular (VV) delay intervals in order to optimize cardiac output. Impedance, preferably sub-threshold impedance, is measured across the heart at selected cardiac cycle times as a measure of chamber expansion or contraction. One embodiment measures impedance over a long AV interval to obtain the minimum impedance, indicative of maximum ventricular expansion, in order to set the AV interval. Another embodiment measures impedance change over a cycle and varies the AV pace interval in a binary search to converge on the AV interval causing maximum impedance change indicative of maximum ventricular output. Another method varies the right ventricle to left ventricle (VV) interval to converge on an impedance maximum indicative of minimum cardiac volume at end systole. Another embodiment varies the VV interval to maximize impedance change.
Abstract:
A method and apparatus are provided for inspecting an electrical defectiveness of a liquid crystal display substrate. The method includes shorting ESD protection devices with a conductive shorting bar to form a current path on each of signal wirings of the substrate, supplying a current to the signal wirings, and determining a defectiveness of the signal wirings depending on the current flowing on the signal wirings.
Abstract:
The present invention relates to bicyclic tetrahydrofuran derivatives of Formula (1) and a preparation method thereof, and particularly it relates to a process of preparing compounds of Formula (1) by performing an intramolecular cyclization of tetrahydrofuran-allenol derivatives in the presence of alcohol compound, transitional metal catalyst and carbon monoxide: wherein n is 1 or 2; R is phenyl optionally substituted with C1-C6 alkyl, C1-C6 alkoxy, hydroxyl or C1-C6 hydroxyalkyl group; and R1 is C1-C6 alkyl group.
Abstract:
An address latch signal generation circuit and an address decoding circuit may generate an address latch signal capable of latching pre-decoded internal address signals. The circuits may include a plurality of address transition detectors, each of the address transition detectors receiving a plurality of internal address signals pre-decoded by a pre-decoder, detecting level transition states of the internal address signals, and generating a control signal which has a predetermined enable period; a first logic unit for performing a logic operation on the control signals received from the plurality of address transition detectors, and generating the result signal; and a latch signal output unit for performing synchronization with a disable time point of the result signal from the first logic unit, thereby generating the address latch signal.