Write circuit of double data rate synchronous DRAM
    12.
    发明申请
    Write circuit of double data rate synchronous DRAM 有权
    双数据速率同步DRAM的写电路

    公开(公告)号:US20050141331A1

    公开(公告)日:2005-06-30

    申请号:US10880381

    申请日:2004-06-29

    Applicant: Yong Cho

    Inventor: Yong Cho

    CPC classification number: G11C7/1093 G11C7/1072 G11C7/1078 G11C7/1096

    Abstract: Provided is a write circuit of a DDR SDRAM, in which a clock domain crossing is generated from a writing driver during a data write operation and a proper data is always transferred to a gio bus line by using the delay of an internal data strobe signal's falling for a certain amount of time as an input data strobe bar signal. Moreover, by using a skew detection circuit, it is possible to detect a skew tDQSS between a clock and a data strobe, and the skew tDQSS is automatically compensated by the skew compensation circuit. From the perspective of a timing error between the clock and the data strobe, therefore, the write operation of the DDR SDRAM has twice the timing margin (0.5tCK) compared to that of the related art. This means that a stable, high-speed write operation of the DDR SDRAM can be made possible.

    Abstract translation: 提供了DDR SDRAM的写入电路,其中在数据写入操作期间从写入驱动器产生时钟域交叉,并且通过使用内部数据选通信号的下降的延迟将适当的数据总是传送到gio总线 作为输入数据选通信号的一定时间。 此外,通过使用偏斜检测电路,可以检测时钟和数据选通之间的偏斜tDQSS,并且由偏斜补偿电路自动补偿偏斜tDQSS。 因此,从时钟与数据选通之间的定时误差的观点出发,与现有技术相比,DDR SDRAM的写操作具有两倍的时间裕度(0.5tCK)。 这意味着可以使DDR SDRAM的稳定的高速写操作成为可能。

    Synthesis of 7-membered carbocyclic compound having diexomethylene groups
    13.
    发明申请
    Synthesis of 7-membered carbocyclic compound having diexomethylene groups 失效
    具有阴离子亚甲基的7-元碳环化合物的合成

    公开(公告)号:US20050059832A1

    公开(公告)日:2005-03-17

    申请号:US10823707

    申请日:2004-04-14

    CPC classification number: C07D493/08

    Abstract: The present invention relates to a synthesis of a 7-membered carbocyclic compound having diexomethylene groups, more particularly to a synthesis of a 7-membered carbocyclic compound having diexomethylene groups, a novel compound having the structure represented by the following Chemical Formula 1, from trimethylsilanylmethyl-allenol derivative by the intramolecular Prins cyclization using Lewis acid. The 7-membered carbocyclic compound is a useful intermediate for synthesis of other multicyclic compounds. In Chemical Formula 1, R1 is a C1 to C6 alkyl group, and R2 and R3 is respectively a hydrogen atom, or R1, R2 and R3 may be connected with neighboring substituents to form a 5 to 10-membered aliphatic or aromatic ring.

    Abstract translation: 本发明涉及具有阴离子亚甲基的7-元碳环化合物的合成,更具体地说,涉及具有下式化学式1所示结构的新化合物,具有三亚甲基硅烷基甲基的三元碳环化合物 通过使用路易斯酸的分子内Prins环化形成的α-烯醇衍生物。 7元碳环化合物是合成其他多环化合物的有用中间体。 在化学式1中,R 1是C 1 -C 6烷基,R 2和R 3分别是氢原子,或者R 1,R 2和R 3可以是 与相邻取代基连接形成5至10元脂族或芳环。

    System and method for estimating duplicate data
    14.
    发明授权
    System and method for estimating duplicate data 有权
    用于估计重复数据的系统和方法

    公开(公告)号:US08793226B1

    公开(公告)日:2014-07-29

    申请号:US11846033

    申请日:2007-08-28

    CPC classification number: G06F17/30156

    Abstract: The present invention provides a system and method for estimating duplicate data in a storage system. A duplicate estimation application executes on a client of a storage system selects an element from an intended destination such as, e.g., a data store of the storage system. If the element is a file (or other data container), the application reads data from the file and computes a fingerprint of the read data. The computed fingerprint is then logged in a fingerprint database, which is illustratively stored on a storage device connected to the client executing the application. This process repeats until the entire file (or other data container) has been read and fingerprinted. Once all elements have been scanned, fingerprinted and recorded, the application identifies any unique entries within the fingerprint database. Utilizing this information, the application computes an estimated space savings that may be realized by employing a data de-duplication technique.

    Abstract translation: 本发明提供一种用于估计存储系统中的重复数据的系统和方法。 在存储系统的客户端上执行的重复估计应用从预期目的地(例如,存储系统的数据存储)中选择一个元素。 如果元素是文件(或其他数据容器),则应用程序从文件读取数据并计算读取数据的指纹。 然后将计算出的指纹记录在指纹数据库中,该指纹数据库被示例性地存储在连接到执行应用程序的客户端的存储设备上。 该过程重复,直到整个文件(或其他数据容器)已被读取和指纹。 一旦所有元素被扫描,指纹和记录,应用程序将识别指纹数据库中的任何唯一条目。 利用该信息,应用程序计算可以通过采用重复数据删除技术来实现的估计空间节省。

    PAVEMENT CRACK CLEANER
    15.
    发明申请

    公开(公告)号:US20120246864A1

    公开(公告)日:2012-10-04

    申请号:US13437510

    申请日:2012-04-02

    Applicant: Yong Cho

    Inventor: Yong Cho

    CPC classification number: E01H11/00 A01M21/02

    Abstract: Devices for cleaning and preparing pavement cracks for sealing are disclosed. An example device comprises a wire brush assembly for removal of mid and large-sized debris, an air blaster for removal of fine-grained particulate, a heat lance, and a vacuum for controlled removal of debris and particulates. The example device would also have means for attachment to an air compressor.

    Abstract translation: 公开了用于清洁和制备用于密封的路面裂纹的装置。 示例性装置包括用于去除中大尺寸碎屑的线刷组件,用于去除细颗粒的空气喷射器,热喷枪和用于控制地去除碎屑和颗粒物的真空。 示例性装置还将具有用于附接到空气压缩机的装置。

    ALGORITHM FOR THE AUTOMATIC DETERMINATION OF OPTIMAL AV AND VV INTERVALS
    17.
    发明申请
    ALGORITHM FOR THE AUTOMATIC DETERMINATION OF OPTIMAL AV AND VV INTERVALS 有权
    用于自动确定最佳AV和VV间隔的算法

    公开(公告)号:US20070213778A1

    公开(公告)日:2007-09-13

    申请号:US11751250

    申请日:2007-05-21

    CPC classification number: A61N1/3627 A61N1/36521 A61N1/3682 A61N1/3684

    Abstract: Methods and devices for determining optimal Atrial to Ventricular (AV) pacing intervals and Ventricular to Ventricular (VV) delay intervals in order to optimize cardiac output. Impedance, preferably sub-threshold impedance, is measured across the heart at selected cardiac cycle times as a measure of chamber expansion or contraction. One embodiment measures impedance over a long AV interval to obtain the minimum impedance, indicative of maximum ventricular expansion, in order to set the AV interval. Another embodiment measures impedance change over a cycle and varies the AV pace interval in a binary search to converge on the AV interval causing maximum impedance change indicative of maximum ventricular output. Another method varies the right ventricle to left ventricle (VV) interval to converge on an impedance maximum indicative of minimum cardiac volume at end systole. Another embodiment varies the VV interval to maximize impedance change.

    Abstract translation: 用于确定最佳心房与心室(AV)起搏间隔和心室间室(VV)延迟间隔的方法和装置,以优化心输出量。 在选择的心脏周期时间内,跨心脏测量阻抗,优选亚阈值阻抗,作为腔室扩张或收缩的量度。 为了设定AV间隔,一个实施例测量长AV间隔上的阻抗以获得指示最大心室扩张的最小阻抗。 另一个实施例测量一个周期的阻抗变化,并且改变二进制搜索中的AV步速间隔以收敛于AV间隔,从而引起指示最大心室输出的最大阻抗变化。 另一种方法将右心室改变为左心室(VV)间隔,以收敛于指示最终心脏收缩最小心脏容积的阻抗最大值。 另一实施例改变VV间隔以最大化阻抗变化。

    Method and apparatus for testing liquid crystal display
    18.
    发明申请
    Method and apparatus for testing liquid crystal display 有权
    液晶显示器测试方法及装置

    公开(公告)号:US20070024315A1

    公开(公告)日:2007-02-01

    申请号:US11541577

    申请日:2006-10-03

    CPC classification number: G09G3/006

    Abstract: A method and apparatus are provided for inspecting an electrical defectiveness of a liquid crystal display substrate. The method includes shorting ESD protection devices with a conductive shorting bar to form a current path on each of signal wirings of the substrate, supplying a current to the signal wirings, and determining a defectiveness of the signal wirings depending on the current flowing on the signal wirings.

    Abstract translation: 提供了一种用于检查液晶显示基板的电气缺陷性的方法和装置。 该方法包括用导电短路棒短路ESD保护装置,以在基板的每个信号布线上形成电流路径,向信号布线提供电流,以及根据在信号上流动的电流来确定信号布线的缺陷 布线。

    ADDRESS LATCH SIGNAL GENERATION CIRCUIT AND ADDRESS DECODING CIRCUIT
    20.
    发明申请
    ADDRESS LATCH SIGNAL GENERATION CIRCUIT AND ADDRESS DECODING CIRCUIT 有权
    地址锁存信号发生电路和地址解码电路

    公开(公告)号:US20060227623A1

    公开(公告)日:2006-10-12

    申请号:US11164723

    申请日:2005-12-02

    Applicant: Yong Cho

    Inventor: Yong Cho

    CPC classification number: G11C11/4087 G11C8/18 G11C11/4082

    Abstract: An address latch signal generation circuit and an address decoding circuit may generate an address latch signal capable of latching pre-decoded internal address signals. The circuits may include a plurality of address transition detectors, each of the address transition detectors receiving a plurality of internal address signals pre-decoded by a pre-decoder, detecting level transition states of the internal address signals, and generating a control signal which has a predetermined enable period; a first logic unit for performing a logic operation on the control signals received from the plurality of address transition detectors, and generating the result signal; and a latch signal output unit for performing synchronization with a disable time point of the result signal from the first logic unit, thereby generating the address latch signal.

    Abstract translation: 地址锁存信号产生电路和地址解码电路可产生能够锁存预解码的内部地址信号的地址锁存信号。 电路可以包括多个地址转换检测器,每个地址转换检测器接收由预解码器预解码的多个内部地址信号,检测内部地址信号的电平转换状态,并产生一个控制信号,该控制信号具有 预定使能期间; 第一逻辑单元,用于对从多个地址转换检测器接收的控制信号执行逻辑运算,并产生结果信号; 以及锁存信号输出单元,用于与来自第一逻辑单元的结果信号的禁用时间点执行同步,从而产生地址锁存信号。

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