公开(公告)号：US20090059664A1

公开(公告)日：2009-03-05

申请号：US12192839

申请日：2008-08-15

申请人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Jung-Ho Moon ,  Soung-Youb Ha

发明人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Jung-Ho Moon ,  Soung-Youb Ha

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C16/06 ,  H01L21/336

CPC分类号： G11C16/0433 ,  G11C16/26 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.

摘要翻译： 在EEPROM单元中读取数据的方法中，用于读取的位线电压被施加到包括存储晶体管和选择晶体管的EEPROM单元。 第一电压被施加到存储晶体管的感测线。 大于第一电压的第二电压被施加到选择晶体管的字线。 将通过EEPROM单元的电流与预定的参考电流进行比较，以读取存储在EEPROM单元中的数据。 可以在擦除状态下增加EEPROM单元的通电池电流，并且可以容易地区分单元中的数据。

公开(公告)号：US20080093646A1

公开(公告)日：2008-04-24

申请号：US11602075

申请日：2006-11-20

申请人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young Ho Kim ,  Myung-Jo Chun

发明人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young Ho Kim ,  Myung-Jo Chun

IPC分类号： H01L29/76

CPC分类号： H01L29/7881 ,  H01L29/66825

摘要： A non-volatile memory device comprises a semiconductor substrate having source/drain regions formed at both ends of a channel region, a gate structure forming an offset region by being separated a predetermined distance from the source region and comprising a charge accumulation region and a control gate sequentially deposited in the channel region to at least partially overlap the drain region, and a spacer arranged at each of both side walls of the gate structure. A threshold voltage value of the offset region changes depending on a dielectric constant of the spacer.

摘要翻译： 一种非易失性存储器件包括：半导体衬底，其具有形成在沟道区两端的源极/漏极区;栅极结构，通过与源极区隔开预定的距离而形成偏移区，并且包括电荷累积区和控制 顺序地沉积在沟道区域中以与漏极区域至少部分重叠的栅极以及布置在栅极结构的两个侧壁中的每一个侧壁处的间隔物。 偏移区域的阈值电压值根据间隔物的介电常数而变化。

公开(公告)号：US20080080244A1

公开(公告)日：2008-04-03

申请号：US11818238

申请日：2007-06-13

申请人： Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

发明人： Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C16/0433 ,  G11C8/10 ,  G11C16/08 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

摘要： A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.

摘要翻译： 非易失性集成电路存储器件可以包括具有相同导电类型的第一和第二电隔离阱的半导体衬底。 可以在第一阱上提供第一多个非易失性存储单元晶体管，并且可以在第二阱上提供第二多个非易失性存储单元晶体管。 本地控制栅极线可以与第一和第二多个非易失性存储单元晶体管电耦合，并且组选择晶体管可以电耦合在本地控制栅极线和全局控制栅极线之间。 更具体地，组选择晶体管可以被配置为响应于施加到组选择晶体管的栅极的组选择栅极信号来电耦合和去耦合本地控制栅极线和全局控制栅极线。 还讨论了相关方法和系统。

公开(公告)号：US20080001204A1

公开(公告)日：2008-01-03

申请号：US11647711

申请日：2006-12-29

申请人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han

发明人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory device and a method for fabricating the non-volatile memory device. The non-volatile memory device includes a memory cell located in a first conductive region and has a memory transistor, a selection transistor and a high voltage switching device located in a second conductive region close to the first conductive region. The memory cell is controlled by the high voltage switching device. At least one of the high voltage switching device, the memory transistor, or the selection transistor has a recessed channel region.

摘要翻译： 一种非易失性存储器件和用于制造非易失性存储器件的方法。 非易失性存储器件包括位于第一导电区域中的存储单元，并且具有位于靠近第一导电区域的第二导电区域中的存储晶体管，选择晶体管和高压开关器件。 存储单元由高电压开关装置控制。 高压开关器件，存储晶体管或选择晶体管中的至少一个具有凹陷沟道区域。

公开(公告)号：US20150155024A1

公开(公告)日：2015-06-04

申请号：US14448717

申请日：2014-07-31

申请人： Bo-Young SEO ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

发明人： Bo-Young SEO ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/1659

摘要： A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

摘要翻译： 磁存储器件包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。 磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。 还描述了相关系统和操作方法。

公开(公告)号：US09330745B2

公开(公告)日：2016-05-03

申请号：US14509756

申请日：2014-10-08

申请人： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

发明人： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

摘要翻译： 磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。 第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。 固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。 磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。 还讨论了相关的操作方法。

公开(公告)号：US20090065845A1

公开(公告)日：2009-03-12

申请号：US12230938

申请日：2008-09-08

申请人： Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

发明人： Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L29/665 ,  H01L29/7833

摘要： Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance.

摘要翻译： 提供了嵌入式半导体器件和制造嵌入式半导体器件的方法。 在制造嵌入式半导体器件的方法中，可以在衬底的单元区域中形成至少一个单元栅极堆叠的层。 逻辑门结构可以形成在衬底的逻辑区域中。 可以在逻辑门结构附近形成第一源极/漏极区，并且可以在逻辑门结构和第一源极/漏极区上形成金属硅化物图案。 可以在至少一个单元栅极堆叠的层上形成至少一个硬掩模，并且可以形成阻挡图案以覆盖逻辑门结构和第一源极/漏极区域。 可以通过使用至少一个硬掩模作为蚀刻掩模来蚀刻至少一个单元栅极堆叠的层而在单元区域中形成至少一个单元栅极堆叠。 单元区域中的存储晶体管可以具有增加的积分度，并且逻辑区域中的逻辑晶体管可以具有增加的响应速度和降低的电阻。

公开(公告)号：US20080179692A1

公开(公告)日：2008-07-31

申请号：US12013618

申请日：2008-01-14

申请人： Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

发明人： Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

IPC分类号： H01L27/112 ,  H01L21/8234

CPC分类号： H01L27/11293 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665

摘要： A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.

摘要翻译： 掩模只读存储器（MROM）器件分别包括形成在衬底的单元和离子区域的第一和第二栅电极。 第一杂质区形成在基板的单电池区域上，以便与第一栅电极相邻。 形成与第一杂质区相同导电类型的第二杂质区，以与第二栅电极的侧壁间隔开。 第四杂质区形成在离电池区域，从第二杂质区延伸并与第二栅电极的侧壁重叠。 第四杂质区域具有与第二杂质区域相反的导电类型，并且深度大于第二杂质区域的深度。

公开(公告)号：US09318181B2

公开(公告)日：2016-04-19

申请号：US14448717

申请日：2014-07-31

申请人： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

发明人： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

IPC分类号： G11C11/00 ,  G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/1659

摘要： A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

摘要翻译： 磁存储装置包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。 磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。 还描述了相关系统和操作方法。

公开(公告)号：US20150179244A1

公开(公告)日：2015-06-25

申请号：US14509756

申请日：2014-10-08

申请人： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

发明人： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

摘要翻译： 磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。 第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。 固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。 磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。 还讨论了相关的操作方法。