公开(公告)号：US07254090B2

公开(公告)日：2007-08-07

申请号：US11340471

申请日：2006-01-27

申请人： Kota Hara ,  Akira Kikutake

发明人： Kota Hara ,  Akira Kikutake

IPC分类号： G11C8/00

CPC分类号： G11C7/1027 ,  G11C11/4076 ,  G11C2207/002

摘要： An internal address generating circuit sequentially generates internal addresses in the burst read operation, with an external address being set as an initial value. A memory core has plural memory cells and sequentially outputs, in response to activation of a column selection signal, data read from the memory cells corresponding to the internal addresses in the burst read operation. In the burst read operation, a column control circuit in a memory core control circuit repeats activation of the column selection signal for a certain period during an activation period of an external control signal and forcibly deactivates the column selection signal in synchronization with deactivation of the external control signal. In the burst read operation, an operation state control circuit in the memory core control circuit deactivates an operation state control signal after a predetermined time has elapsed from the deactivation of the external control signal.

公开(公告)号：US06288585B1

公开(公告)日：2001-09-11

申请号：US09535745

申请日：2000-03-27

申请人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

发明人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

摘要翻译： 接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动， 控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号 到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。

公开(公告)号：US08724425B2

公开(公告)日：2014-05-13

申请号：US13398495

申请日：2012-02-16

申请人： Kota Hara

发明人： Kota Hara

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/06 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4082

摘要： A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.

摘要翻译： 一种半导体存储装置，包括提供第一信号的外部端子，核心电路以及访问操作控制电路，其基于第一信号的脉冲宽度生成指示到核心电路的接入操作模式的信号，用于后续周期 信号。

公开(公告)号：US07697367B2

公开(公告)日：2010-04-13

申请号：US12146962

申请日：2008-06-26

申请人： Kota Hara

发明人： Kota Hara

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4087 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal.

摘要翻译： 半导体存储器件包括存储块，将主字线设置为第一电位用于激活的主字解码器，第二电位或第三电位的电路，用于产生以间隔指示定时的循环信号的电路，块选择 选择要访问的存储器块的电路，连续选择电路，用于依次选择存储器块;以及电路，被配置为控制主字解码器，使得由所述存储器块选择的存储器块的未选择的主字线 块选择电路被设置为第三电位，使得所选择的存储块的主字线在访问之后保持在第三电位，并且使得由连续选择电路选择的存储块的主字线被设置 在由循环信号指示的定时处于第二电位。

公开(公告)号：US07252897B2

公开(公告)日：2007-08-07

申请号：US10653429

申请日：2003-09-03

申请人： Koichi Shimokawa ,  Kota Hara

发明人： Koichi Shimokawa ,  Kota Hara

IPC分类号： G11B5/725

CPC分类号： G11B5/725 ,  G11B5/8408

摘要： A magnetic recording disk having a substrate, a magnetic layer formed on the substrate, a protective layer formed on the magnetic layer and a lubricant layer formed on the protective layer, the lubricant layer containing a perfluoropolyether compound having an end moiety containing a phosphazene ring and a perfluoropolyether compound having an end moiety containing a hydroxyl group, or the lubricant layer containing a perfluoropolyether compound having an end moiety containing a hydroxyl group on the protective layer side and a perfluoropolyether compound having an end moiety containing a phosphazene ring on the other surface side, and a process for manufacturing each of these magnetic recording disks.

公开(公告)号：US08274854B2

公开(公告)日：2012-09-25

申请号：US13330456

申请日：2011-12-19

申请人： Kota Hara

发明人： Kota Hara

IPC分类号： G11C7/00

CPC分类号： G11C29/48 ,  G11C7/20 ,  G11C7/22 ,  G11C11/40 ,  G11C11/401 ,  G11C11/40615 ,  G11C11/4072 ,  G11C29/08 ,  G11C29/1201

摘要： A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.

摘要翻译： 半导体存储装置包括定时控制电路，其生成用于控制读取操作和写入操作中的至少一个的信号; 输入信号垫; 多个控制信号焊盘; 以及耦合到所述多个控制信号焊盘中的至少一个的开关电路。 开关电路在第一模式中基于来自输入信号焊盘的信号产生要提供给定时控制电路的第一控制信号。

公开(公告)号：US08139438B2

公开(公告)日：2012-03-20

申请号：US12412092

申请日：2009-03-26

申请人： Kota Hara

发明人： Kota Hara

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/06 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4082

摘要： A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.

摘要翻译： 一种半导体存储装置，包括提供第一信号的外部端子，核心电路以及访问操作控制电路，其基于第一信号的脉冲宽度生成指示到核心电路的接入操作模式的信号，用于后续周期 信号。

公开(公告)号：US20050265116A1

公开(公告)日：2005-12-01

申请号：US10994632

申请日：2004-11-23

申请人： Kota Hara ,  Shinichi Yamada

发明人： Kota Hara ,  Shinichi Yamada

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C7/20 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/4072

摘要： A semiconductor memory device, in which a burst operation is performed using a memory core, has a read/write trigger signal generating circuit and a read/write signal generating circuit. The read/write trigger signal generating circuit generates a read/write signal request from a predetermined timing signal during the burst operation. The read/write signal generating circuit receives an output signal from the read/write trigger signal generating circuit and outputs a read/write signal after a core operation just prior to receipt of the output signal is complete and the subsequent activation of a row side is complete.

摘要翻译： 使用存储器核进行突发操作的半导体存储器件具有读/写触发信号生成电路和读/写信号生成电路。 读/写触发信号产生电路在脉冲串操作期间从预定定时信号产生读/写信号请求。 读/写信号发生电路在读/写触发信号产生电路接收输出信号，并且在接收到输出信号完成之后在核心操作之后输出读/写信号，并且随后的行侧激活 完成。

公开(公告)号：US06318707B1

公开(公告)日：2001-11-20

申请号：US09536467

申请日：2000-03-28

申请人： Kota Hara ,  Hiroyoshi Tomita ,  Naoharu Shinozaki

发明人： Kota Hara ,  Hiroyoshi Tomita ,  Naoharu Shinozaki

IPC分类号： G11C800

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/225

摘要： A semiconductor integrated circuit device includes a clock buffer circuit receiving a clock signal, a data buffer circuit receiving a data signal, an output circuit outputting the data signal from the data buffer circuit in accordance with the clock signal from the clock buffer circuit, and an adjustment circuit adjusting timings of the clock signal and the data signals.

摘要翻译： 一种半导体集成电路装置，包括接收时钟信号的时钟缓冲电路，接收数据信号的数据缓冲电路，根据来自时钟缓冲器电路的时钟信号从数据缓冲电路输出数据信号的输出电路，以及 调整电路调整时钟信号和数据信号的定时。

公开(公告)号：US07672181B2

公开(公告)日：2010-03-02

申请号：US12130578

申请日：2008-05-30

申请人： Kaoru Mori ,  Kota Hara ,  Jun Ohno

发明人： Kaoru Mori ,  Kota Hara ,  Jun Ohno

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/025 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2211/4061

摘要： Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.

摘要翻译： 每个子字线耦合到存储器单元的转移晶体管的栅极。 当主字线处于激活电平时，子字解码器的第一开关将子字线耦合到高电平电压线。 当主字线处于钝化级别时，第二开关将子字线耦合到低电平电压线。 当字复位信号线处于激活电平时，第三开关将子字线耦合到低电平电压线。 复位控制电路在测试模式期间禁用主字线的失活或字复位信号线的激活。 第二和第三开关中的一个被强制关闭，从而可以容易地检测到子字解码器的操作故障。