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149 条记录 (耗时 0.025 秒)

    Resistance change memory
    11.
    发明授权
    Resistance change memory 有权
    电阻变化记忆

    公开(公告)号：US08189363B2

    公开(公告)日：2012-05-29

    申请号：US12543793

    申请日：2009-08-19

    申请人： Kenji Tsuchida ,  Yoshihiro Ueda

    发明人： Kenji Tsuchida ,  Yoshihiro Ueda

    IPC分类号： G11C11/00 ,  G11C7/02

    CPC分类号： G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

    摘要： A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit.

    摘要翻译： 电阻变化存储器包括两个存储单元阵列，每个存储单元阵列包括多个存储单元，存储单元包括可变电阻元件，分别提供给两个存储单元阵列的两个参考单元阵列，每个参考单元阵列包括多个参考单元， 所述参考单元具有参考值，以及由所述两个存储单元阵列共享的读出放大器，并且通过使用与包括所述存储单元阵列的第一存储单元阵列不同的第二存储单元阵列对应的参考单元阵列来检测所访问的存储器单元中的数据 存取存储单元 在读取数据时，一个参考单元阵列中的特定参考单元总是基于一个存储单元阵列作为单元而被激活用于地址空间。

    Speed changing transmission apparatus
    12.
    发明授权
    Speed changing transmission apparatus 有权
    变速传动装置

    公开(公告)号：US08172714B2

    公开(公告)日：2012-05-08

    申请号：US12281719

    申请日：2007-09-25

    申请人： Shoso Ishimori ,  Yoshiyuki Katayama ,  Yoshihiro Ueda ,  Shinichi Morita ,  Shinichi Kawabata ,  Shigeki Hayashi ,  Masaaki Nishinaka ,  Takayasu Kobayashi ,  Go Takagi

    发明人： Shoso Ishimori ,  Yoshiyuki Katayama ,  Yoshihiro Ueda ,  Shinichi Morita ,  Shinichi Kawabata ,  Shigeki Hayashi ,  Masaaki Nishinaka ,  Takayasu Kobayashi ,  Go Takagi

    IPC分类号： F16H3/72 ,  F16H37/06 ,  F16H47/04 ,  F16H3/44 ,  B60K17/06

    CPC分类号： F16H47/04 ,  F16H2037/088 ,  F16H2037/0886 ,  F16H2200/201

    摘要： A composite planetary transmission section (P) is provided for synthesizing output from a stepless speed changing section (20) with an engine drive force. In a transmission line from the planetary transmission section (P) to an output rotational body (90), there are provided first clutch mechanism (60), a second clutch mechanism (70), a speed-reducing planetary transmission mechanism (80), an operable coupling clutch mechanism (110) and an output clutch mechanism (120). A ring gear (83) of the speed-reducing planetary transmission mechanism (80) includes a brake mechanism (100). A sun gear (43) of the planetary transmission section (P), an input side rotational member (62) of the first clutch mechanism (60), an input side rotational member (71) of the second clutch mechanism (70), a sun gear (84) of the speed-reducing planetary transmission mechanism (80), and an input side rotational member (122) of the output clutch mechanism (120) are rotatable about a common rotational axis. A rotational shaft (97) operably coupling a carrier (44) of the composite planetary transmission section (P) with the output rotational body (90) is inserted through a planetary transmission mechanism (50) of the composite planetary transmission section (P), the first clutch mechanism (60), the second clutch mechanism (70) and the speed-reducing planetary transmission mechanism (80).

    摘要翻译： 复合行星传动部分（P）用于合成来自无级变速部分（20）的输出与发动机驱动力。 在从行星传动部（P）到输出旋转体（90）的传输线中，设置有第一离合器机构（60），第二离合器机构（70），减速行星传动机构（80） 可操作的联接离合器机构（110）和输出离合器机构（120）。 减速行星传动机构（80）的齿圈（83）包括制动机构（100）。 行星传动部（P）的太阳齿轮（43），第一离合器机构（60）的输入侧旋转部件（62），第二离合器机构（70）的输入侧旋转部件（71） 减速行星传动机构80的太阳齿轮（84）和输出离合器机构（120）的输入侧旋转部件（122）能够绕公共旋转轴线旋转。 通过复合行星传动部（P）的行星传动机构（50）插入将复合行星传动部（P）的托架（44）与输出转动体（90）可操作地连接的旋转轴（97） 第一离合器机构（60），第二离合器机构（70）和减速行星传动机构（80）。

    SEMICONDUCTOR MEMORY DEVICE
    13.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20110235402A1

    公开(公告)日：2011-09-29

    申请号：US13053041

    申请日：2011-03-21

    申请人： Yoshihiro Ueda

    发明人： Yoshihiro Ueda

    IPC分类号： G11C11/21

    CPC分类号： G11C11/1653 ,  G11C7/14 ,  G11C8/14 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0042

    摘要： According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target.

    摘要翻译： 根据一个实施例，半导体存储器件包括第一单元阵列，其包括存储单元和参考单元，在第一方向上与第一单元阵列相邻的第二单元阵列，位于第一单元阵列附近的第三单元阵列 与第二方向相邻的第四单元阵列，以及连接到第一至第四单元阵列的读出放大器，用于将通过存储单元的电流与通过第一方向的电流进行比较 参考单元以确定存储单元的数据。 从与作为读取目标的单元阵列对角地相对的单元阵列中选择参考单元。

    Semiconductor memory device
    14.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08014219B2

    公开(公告)日：2011-09-06

    申请号：US12552219

    申请日：2009-09-01

    申请人： Yoshihiro Ueda

    发明人： Yoshihiro Ueda

    IPC分类号： G11C7/00

    CPC分类号： G11C13/004 ,  G11C7/062 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2013/0054 ,  G11C2213/31 ,  G11C2213/32

    摘要： A semiconductor memory device includes a memory cell having a resistance which differs based on stored data, a bit line connected to the memory cell, a first MOSFET which clamps the bit line to a read voltage when reading data, a sense amplifier which detects the stored data in the memory cell based on a current flowing through the bit line, a first switch element which connects the sense amplifier to a drain of the first MOSFET, a second switch element which connects a source of the first MOSFET to the bit line, a third switch element which connects the drain of the first MOSFET to a ground terminal, and a fourth switch element which connects the source of the first MOSFET to a ground terminal.

    摘要翻译： 半导体存储器件包括存储单元，该存储单元具有基于存储数据而不同的电阻，连接到存储单元的位线，读取数据时将位线钳位到读取电压的第一MOSFET;检测放大器 基于流过位线的电流存储单元中的数据，将读出放大器连接到第一MOSFET的漏极的第一开关元件，将第一MOSFET的源极连接到位线的第二开关元件， 第三开关元件，其将第一MOSFET的漏极连接到接地端子;以及第四开关元件，其将第一MOSFET的源极连接到接地端子。

    Semiconductor memory device
    15.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07995379B2

    公开(公告)日：2011-08-09

    申请号：US12396559

    申请日：2009-03-03

    申请人： Yoshihiro Ueda

    发明人： Yoshihiro Ueda

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16 ,  G11C7/062 ,  G11C7/065 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/1204 ,  G11C2029/5006

    摘要： A semiconductor memory device includes a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other, a first MOSFET having a drain terminal connected with the first node, a second MOSFET having a drain terminal connected with the second node, a memory cell connected with a source terminal of the first MOSFET, and a reference cell. The semiconductor memory device further includes a connection control circuit that connects a source terminal of the second MOSFET with the reference cell at the time of a regular operation and connects the source terminal of the second MOSFET with a reference voltage terminal at the time of a test operation.

    摘要翻译： 半导体存储器件包括：读出放大器，其将流过第一节点和第二节点的电流的强度相互比较;第一MOSFET，具有与第一节点连接的漏极端子;第二MOSFET，漏极端子与第二节点连接;第二MOSFET， 节点，与第一MOSFET的源极端子连接的存储单元和参考单元。 半导体存储器件还包括连接控制电路，其在正常操作时将第二MOSFET的源极端子与参考单元连接，并且在测试时将第二MOSFET的源极端子与参考电压端子连接 操作。

    Magnetoresistive random access memory
    16.
    发明授权
    Magnetoresistive random access memory 有权
    磁阻随机存取存储器

    公开(公告)号：US07791930B2

    公开(公告)日：2010-09-07

    申请号：US12164410

    申请日：2008-06-30

    申请人： Yoshihiro Ueda

    发明人： Yoshihiro Ueda

    IPC分类号： G11C11/00 ,  G11C5/08 ,  G11C11/14

    CPC分类号： G11C11/15 ,  G11C11/1673

    摘要： A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element.

    摘要翻译： MRAM包括采用低和高电阻状态的第一磁阻效应（MR）元件。 第二MR元件固定为低电阻或高电阻状态。 第一和第二MOSFET分别连接到第一和第二MR元件。 读出放大器放大流经第一和第二MOSFET的电流值之差。 电流电路输出其值位于流过低电阻状态和高电阻状态的第一MR元件的电流之间的参考电流。 第三个MOSFET的一端接收参考电流并连接到其自己的栅极端子。 第二MOSFET的栅极端子接收与第三MOSFET的栅极端子相同的电位。 第一电阻元件连接到第三MOSFET的另一端，并且具有与第二磁阻效应元件相同的电阻。

    Magnetoresistive random access memory and method of manufacturing the same
    18.
    发明授权
    Magnetoresistive random access memory and method of manufacturing the same 失效
    磁阻随机存取存储器及其制造方法

    公开(公告)号：US07772660B2

    公开(公告)日：2010-08-10

    申请号：US12119720

    申请日：2008-05-13

    申请人： Yoshihiro Ueda

    发明人： Yoshihiro Ueda

    IPC分类号： H01L29/82 ,  H01L43/00

    CPC分类号： G11C11/16 ,  B82Y10/00 ,  H01L27/228

    摘要： A magnetic random access memory includes a transistor having a gate electrode formed above a surface of a substrate, and first and second impurity diffusion regions which sandwich a channel region below the gate electrode, a first plug formed on the first impurity diffusion region, a recording element formed on the first plug, including a plurality of stacked layers, and configured to hold information in accordance with an internal magnetization state, a first signal line formed on the recording element, a second plug formed on the second impurity diffusion region, an electrical conductor formed on the second plug, an area of a shape of the electrical conductor, which is projected onto the surface of the substrate, being larger than that of a shape of the recording element, which is projected onto the surface of the substrate, and a second signal line formed on the electrical conductor.

    摘要翻译： 磁性随机存取存储器包括晶体管，其具有形成在衬底表面上的栅电极，以及夹在栅电极下方的沟道区的第一和第二杂质扩散区，形成在第一杂质扩散区上的第一插塞， 元件，形成在第一插头上，包括多个堆叠层，并且被配置为根据内部磁化状态保存信息，形成在记录元件上的第一信号线，形成在第二杂质扩散区上的第二插塞，电 导体形成在第二插头上，突出到基板的表面上的电导体的形状的面积大于投影到基板的表面上的记录元件的形状， 形成在电导体上的第二信号线。