公开(公告)号：US07629653B1

公开(公告)日：2009-12-08

申请号：US11827765

申请日：2007-07-13

Applicant: Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

Inventor： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

IPC: H01L29/78

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

Abstract translation: 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2或H 2 O），从而改善晶体管的负偏压温度不稳定性（NBTI）寿命。

公开(公告)号：US20090243001A1

公开(公告)日：2009-10-01

申请号：US12080166

申请日：2008-03-31

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy

IPC: H01L29/00 ,  H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/3145

Abstract: Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.

Abstract translation: 重复沉积和退火操作以将沉积破坏成多个顺序的沉积退火操作以达到期望的退火介电层厚度。 在一个具体实施方案中，进行包括NH 3或ND 3环境，随后是N 2 O或NO环境的两步退火。 在一个实施例中，采用这种方法形成具有仅通过沉积工艺可获得的化学计量但具有均匀材料质量的电介质层，这在沉积过程中具有非常高的特性。 在特定实施例中，顺序沉积 - 退火操作提供退火的第一介电层，第二介电层可以在其上基本上保持不退火。

公开(公告)号：US20090011609A1

公开(公告)日：2009-01-08

申请号：US12197466

申请日：2008-08-25

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

IPC: H01L21/28

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.

Abstract translation: 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括提供其上设置有电荷捕获层的衬底。 然后通过将电荷捕获层暴露于自由基氧化过程，电荷俘获层的一部分被氧化以形成电荷俘获层上方的阻挡电介质层。

公开(公告)号：US07192839B1

公开(公告)日：2007-03-20

申请号：US10848638

申请日：2004-05-19

Applicant: Krishnaswamy Ramkumar ,  Sharmin Sadoughi

Inventor： Krishnaswamy Ramkumar ,  Sharmin Sadoughi

IPC: H01L23/544

CPC classification number: H01L21/76229 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.

Abstract translation: 公开了一种包括半导体衬底，半导体衬底中的隔离沟槽和半导体衬底中的对准沟槽的半导体结构。 该结构还包括电介质层和金属层。 介电层位于半导体衬底上并且在隔离沟槽和对准沟槽中。 电介质层填充隔离沟槽并且不填充对准沟槽。 金属层位于电介质层上。

公开(公告)号：US07042054B1

公开(公告)日：2006-05-09

申请号：US10740205

申请日：2003-12-18

Applicant: Krishnaswamy Ramkumar ,  Frederick B. Jenne

Inventor： Krishnaswamy Ramkumar ,  Frederick B. Jenne

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/3003 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

Abstract: A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.

Abstract translation: 提供了一种用于处理半导体形貌的方法，其包括在氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的一个或多个界面上扩散氘。 特别地，该方法可以包括在SONOS结构之间隔开的电介质层的回流期间扩散氘穿过SONOS结构的一个或多个界面。 在一些实施方案中，该方法可以包括在回流工艺之前在SONOS结构之上形成去氢化氮化物层。 另外或替代地，该方法可以包括在回流工艺之前在SONOS结构内形成一个去氢化氮化物层。 在一些情况下，该方法可以进一步包括在形成去氢化氮化物层之前用缺失的物质退火SONOS结构。 在任一实施例中，可以形成SONOS结构，其包括排列在硅层和该结构的氧化物层的界面内的氘。

公开(公告)号：US07018942B1

公开(公告)日：2006-03-28

申请号：US10988813

申请日：2004-11-15

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

IPC: H01L21/469

CPC classification number: H01L23/5222 ,  H01L21/76837 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

公开(公告)号：US06905893B1

公开(公告)日：2005-06-14

申请号：US10289020

申请日：2002-11-05

Applicant: Sundar Narayanan ,  Krishnaswamy Ramkumar

Inventor： Sundar Narayanan ,  Krishnaswamy Ramkumar

IPC: G01N1/32 ,  G01N19/06 ,  H01L21/66 ,  H01L23/544

CPC classification number: H01L22/20 ,  G01N1/32 ,  G01N19/06 ,  H01L22/34

Abstract: A method is provided for determining a concentration profile of an impurity within a layer of a semiconductor topography. The method may include exposing the layer and an underlying layer to oxidizing conditions. In addition, the method may include comparing thickness measurements of total dielectric above the underlying layer taken before and after exposing the topography to oxidizing conditions . In some cases, the comparison may include plotting pre-oxidation thickness measurements versus post-oxidation measurements. In other embodiments, the comparison may include determining differences between the pre-oxidation and post-oxidation thickness measurements and correlating the differences to concentrations of the impurity. In some cases, such a correlation may include subtracting a concentration of the impurity at a first location along the semiconductor topography from a concentration of the impurity at a second location along the semiconductor topography.

Abstract translation: 提供了一种用于确定半导体形貌层内的杂质的浓度分布的方法。 该方法可以包括将层和下层暴露于氧化条件。 此外，该方法可以包括将暴露于地形之前和之后的所述下层的总电介质的厚度测量值与氧化条件进行比较。 在某些情况下，比较可能包括绘制预氧化厚度测量值与氧化后测量值。 在其他实施例中，比较可以包括确定预氧化和后氧化厚度测量之间的差异并将差异与杂质的浓度相关联。 在一些情况下，这种相关可以包括沿着半导体形貌从第二位置处的杂质浓度减去沿着半导体形貌的第一位置处的杂质的浓度。

公开(公告)号：US06903002B1

公开(公告)日：2005-06-07

申请号：US10241236

申请日：2002-09-11

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Christopher A. Seams ,  Thurman J. Rodgers

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Christopher A. Seams ,  Thurman J. Rodgers

IPC: H01L21/302 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/7682

Abstract: In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.

Abstract translation: 在一个实施例中，金属层包括多条金属线。 低k电介质沉积在金属层上，使得气隙至少形成在两条金属线之间。 低k介质的相对较低的介电常数降低金属线上的电容，而不管是否形成气隙。 低k电介质中的气隙进一步降低了金属线路上的电容。 减小的电容转换为较低的RC延迟和更快的信号传播速度。

公开(公告)号：US06828201B1

公开(公告)日：2004-12-07

申请号：US10054515

申请日：2001-10-22

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L218236

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A method of forming a top oxide layer of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include forming an in situ steam generation (ISSG) top oxide layer 208 from a charge storing dielectric layer 206 by reacting hydrogen and oxygen on a wafer surface (step 102) and depositing a conductive gate layer 210 (step 104). An ISSG top oxide layer 208 may be of higher quality and formed with a smaller thermal budget than conventional approaches.

Abstract translation: 公开了一种形成SONOS型非易失性存储装置的顶部氧化物层的方法。 根据第一实施例，一种方法可以包括通过使晶片表面上的氢和氧反应，从电荷存储电介质层206形成原位蒸汽产生（ISSG）顶部氧化物层208（步骤102），并沉积导电栅极层210 （步骤104）。 ISSG顶部氧化物层208可以具有更高的质量并且具有比常规方法更小的热预算。

公开(公告)号：US06774033B1

公开(公告)日：2004-08-10

申请号：US10287258

申请日：2002-11-04

Applicant: Mira Ben-Tzur ,  Dafna Beery ,  Gorley L. Lau ,  Krishnaswamy Ramkumar

Inventor： Mira Ben-Tzur ,  Dafna Beery ,  Gorley L. Lau ,  Krishnaswamy Ramkumar

IPC: H01L214763

CPC classification number: H01L21/32051 ,  H01L21/76895

Abstract: In one embodiment, a local interconnect layer in an integrated circuit is formed by depositing a first film over an oxide layer and depositing a second film over the first film. The first film may comprise titanium nitride, while the second film may comprise tungsten, for example. The first film and the second film may be deposited in-situ by sputtering. The second film may be etched using the first film as an etch stop, and the first film may be etched using the oxide layer as an etch stop.

Abstract translation: 在一个实施例中，通过在氧化物层上沉积第一膜并在第一膜上沉积第二膜来形成集成电路中的局部互连层。 第一膜可以包括氮化钛，而第二膜可以包括例如钨。 第一膜和第二膜可以通过溅射原位沉积。 可以使用第一膜作为蚀刻停止来蚀刻第二膜，并且可以使用氧化物层作为蚀刻停止来蚀刻第一膜。