公开(公告)号：US20140319540A1

公开(公告)日：2014-10-30

申请号：US14258251

申请日：2014-04-22

申请人： Masahiro SUGIMOTO

发明人： Masahiro SUGIMOTO

IPC分类号： H01L27/16

CPC分类号： H01L29/0653 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7804

摘要： A semiconductor device is provided with a semiconductor substrate in which a power semiconductor element part and a temperature sensing diode part are provided. The temperature sensing diode part includes a first semiconductor region, a second semiconductor region, a first base region, and a first drift region. In the semiconductor substrate, an isolation trench is formed, which passes through the first base region, extends to the first drift region, and surrounds an outer periphery of the temperature sensing diode part. At least a part of one of side walls of the isolation trench is in contact with the power semiconductor element part, and the other side wall of the isolation trench is in contact with the temperature sensing diode part.

摘要翻译： 半导体器件设置有半导体衬底，其中提供功率半导体元件部分和温度感测二极管部分。 温度感测二极管部分包括第一半导体区域，第二半导体区域，第一基极区域和第一漂移区域。 在半导体衬底中，形成隔离沟槽，其通过第一基极区域延伸到第一漂移区域并且包围温度感测二极管部件的外周。 隔离沟槽的一个侧壁的至少一部分与功率半导体元件部分接触，并且隔离沟槽的另一个侧壁与温度感测二极管部分接触。

公开(公告)号：US20100295098A1

公开(公告)日：2010-11-25

申请号：US12822328

申请日：2010-06-24

申请人： Masahiro SUGIMOTO ,  Tetsu KACHI ,  Yoshitaka NAKANO ,  Tsutomu UESUGI ,  Hiroyuki UEDA ,  Narumasa SOEJIMA

发明人： Masahiro SUGIMOTO ,  Tetsu KACHI ,  Yoshitaka NAKANO ,  Tsutomu UESUGI ,  Hiroyuki UEDA ,  Narumasa SOEJIMA

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/778 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

摘要翻译： 半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。 此外，SI-GaN层的杂质浓度小于1×1017cm-3。 包括III-V半导体的半导体器件可以具有稳定的常关断操作。

公开(公告)号：US20100044753A1

公开(公告)日：2010-02-25

申请号：US12544451

申请日：2009-08-20

申请人： Masahiro SUGIMOTO ,  Hiroyuki Ueda ,  Tsutomu Uesugi ,  Masakazu Kanechika ,  Tetsu Kachi

发明人： Masahiro SUGIMOTO ,  Hiroyuki Ueda ,  Tsutomu Uesugi ,  Masakazu Kanechika ,  Tetsu Kachi

IPC分类号： H01L29/205 ,  H01L29/78

CPC分类号： H01L29/2003 ,  H01L21/28264 ,  H01L29/41766 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7787 ,  H01L29/7788

摘要： A nitride semiconductor device 2 comprises a nitride semiconductor layer 10. A gate insulating film 16 is formed on the surface of the nitride semiconductor layer 10. The gate insulating film 16 includes a portion composed of an aluminum nitride film 15 and a portion composed of an insulating material 14 that contains at least one of oxygen or silicon. A region W2 of the nitride semiconductor layer 10 facing the aluminum nitride film 15 is included in a region W1 of the nitride semiconductor layer 10 facing a gate electrode 18. The nitride semiconductor device 2 may further comprise a nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may be stacked on the surface of the nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may have a larger band gap than that of the nitride semiconductor lower layer 8 and have a heterojunction formed there between.

摘要翻译： 氮化物半导体器件2包括氮化物半导体层10.栅极绝缘膜16形成在氮化物半导体层10的表面上。栅极绝缘膜16包括由氮化铝膜15构成的部分和由 包含氧或硅中的至少一种的绝缘材料14。 面向氮化铝膜15的氮化物半导体层10的区域W2包含在氮化物半导体层10的面向栅极电极18的区域W1中。氮化物半导体器件2还可以包括氮化物半导体下层8.氮化物半导体层 半导体层10可以堆叠在氮化物半导体下层8的表面上。氮化物半导体层10可以具有比氮化物半导体下层8更大的带隙，并且在其间形成异质结。

公开(公告)号：US20100038681A1

公开(公告)日：2010-02-18

申请号：US12540230

申请日：2009-08-12

申请人： Masahiro SUGIMOTO ,  Tat-Sing Paul Chow ,  Zhongda Li ,  Totsu Kachi ,  Tsutomu Uesugi

发明人： Masahiro SUGIMOTO ,  Tat-Sing Paul Chow ,  Zhongda Li ,  Totsu Kachi ,  Tsutomu Uesugi

IPC分类号： H01L29/778

CPC分类号： H01L29/7787 ,  H01L29/0642 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7788

摘要： An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.

摘要翻译： 公开了一种HEMT型晶体管，其是常闭型，栅极阈值电压的变化小。 晶体管设置有p型区域，势垒区域，绝缘膜，栅极电极。 沟道区域连接到p型区域的上表面。 通道区域是n型或i型，并且设置有第一通道区域和第二通道区域。 阻挡区域与第一通道区域的上表面形成异质结。 绝缘膜连接到第二通道区域的上表面和阻挡区域的上表面。 栅电极经由绝缘膜面向第二沟道区和阻挡区。 第一通道区域和第二通道区域在电流通路中串联布置。

公开(公告)号：US20080142845A1

公开(公告)日：2008-06-19

申请号：US12000528

申请日：2007-12-13

申请人： Masahito KODAMA ,  Eiko HAYASHI ,  Tsutomu UESUGI ,  Masahiro SUGIMOTO

发明人： Masahito KODAMA ,  Eiko HAYASHI ,  Tsutomu UESUGI ,  Masahiro SUGIMOTO

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/78 ,  H01L29/7827

摘要： A HEMT has a drain region adapted to be electrically connected to a high voltage of an electric source, a source region adapted to be electrically connected to a low voltage of the electric source. A first semiconductor region is disposed between the drain region and the source region. A MIS structure and a heterostructure are disposed at a surface of the first semiconductor region. The MIS structure includes a gate electrode that faces a portion of a surface of the first semiconductor region with a gate insulating membrane therebetween. The heterostructure includes a second semiconductor region which makes contact with a rest portion of the surface of the first semiconductor region and has a wider band-gap than the first semiconductor region. The drain region and the source region are capable of being electrically connected with a structure in which the MIS structure 40 and the heterostructure are arranged in series.

摘要翻译： HEMT具有适于电连接到电源的高电压的漏极区域，适于电连接到电源的低电压的源极区域。 第一半导体区域设置在漏极区域和源极区域之间。 MIS结构和异质结构设置在第一半导体区域的表面。 MIS结构包括栅电极，其面对第一半导体区域的表面的一部分，栅极绝缘膜在其间。 异质结构包括与第一半导体区域的表面的其余部分接触并且具有比第一半导体区域更宽的带隙的第二半导体区域。 漏极区域和源极区域能够与MIS结构40和异质结构串联布置的结构电连接。

公开(公告)号：US20080105954A1

公开(公告)日：2008-05-08

申请号：US11976451

申请日：2007-10-24

申请人： Masahito KODAMA ,  Eiko HAYASHI ,  Masahiro SUGIMOTO

发明人： Masahito KODAMA ,  Eiko HAYASHI ,  Masahiro SUGIMOTO

IPC分类号： H01L29/06 ,  H01L21/306

CPC分类号： H01L29/7813 ,  H01L21/32134 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/432 ,  H01L29/66734 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8613 ,  H01L33/24 ,  H01L33/382 ,  H01S5/0421 ,  H01S5/32341

摘要： A group III nitride based semiconductor device which has a trench or mesa structure and of which leakage of current and reduction of breakdown voltage are prevented. A GaN layer 2 was grown on a C-plane sapphire substrate 1, and a T-shaped USG film 3 was formed on the GaN layer 2 so that side surfaces of the USG film 3 were arranged parallel to A-plane and M-plane of the GaN layer 2. Thereafter, by using the USG film 3 as a mask, the GaN layer 2 was dry-etched. As is clear from FIGS. 2A and 2B, the M-plane is less roughened as compared with the A-plane. Subsequently, wet-etched was performed by use of an aqueous TMAH solution. As is clear from FIGS. 2C and 2D, roughness of the A-plane and the M-plane are removed, and, particularly, the M-plane assumes a mirror surface. Thus, through provision of M-plane side surfaces of a trench or an etching-formed mesa, leakage of current and reduction of breakdown voltage of a group III nitride based semiconductor device can be prevented.

摘要翻译： 具有沟槽或台面结构，并且防止电流泄漏和击穿电压降低的III族氮化物基半导体器件。 在C面蓝宝石衬底1上生长GaN层2，在GaN层2上形成T形USG膜3，使得USG膜3的侧面平行于A面和M面 的GaN层2。 此后，通过使用USG膜3作为掩模，对GaN层2进行干式蚀刻。 从图 如图2A和2B所示，与A平面相比，M平面不那么粗糙。 随后，使用TMAH水溶液进行湿蚀刻。 从图 如图2C和2D所示，去除了A平面和M面的粗糙度，特别地，M平面呈现镜面。 因此，通过设置沟槽的M面侧面或蚀刻形成的台面，可以防止III族氮化物类半导体器件的漏电流和击穿电压的降低。