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33 条记录 (耗时 0.045 秒)

    SIGNAL CIRCUIT AND INFORMATION PROCESSING APPARATUS HAVING THE SAME
    11.
    发明申请
    SIGNAL CIRCUIT AND INFORMATION PROCESSING APPARATUS HAVING THE SAME 审中-公开
    信号电路和信息处理装置

    公开(公告)号：US20090067103A1

    公开(公告)日：2009-03-12

    申请号：US11912517

    申请日：2006-04-26

    申请人： Masato Kijima ,  Osamu Hikino ,  Takashi Shiba

    发明人： Masato Kijima ,  Osamu Hikino ,  Takashi Shiba

    IPC分类号： H02H9/00 ,  H03H9/72

    CPC分类号： H04B1/0057 ,  H04B1/48

    摘要： A high-frequency appliance, which is allowed to have an ESD tolerance by using a small-sized and low-cost ESD protection circuit, and in particular, an antenna duplexer having a multi-band high-frequency switch function. There are provided a signal separation unit for separating a first frequency band signal from a second frequency band signal, the second frequency band being lower than the first frequency band, a first SAW filter for inputting the first frequency band signal outputted from the signal separation unit, a second SAW filter for inputting the second frequency band signal outputted from the signal separation unit, and a high-pass filter for permitting passing of the second frequency band signal, and limiting passing of a signal whose frequency band is lower than the second frequency band, the high-pass filter being located on a signal line connecting the signal separation unit and the second SAW filter to each other.

    摘要翻译： 通过使用小型和低成本的ESD保护电路，允许具有ESD容限的高频器件，特别是具有多频带高频开关功能的天线双工器。 提供了一种信号分离单元，用于将第一频带信号与第二频带信号分离，第二频带低于第一频带;第一SAW滤波器，用于输入从信号分离单元输出的第一频带信号 ，用于输入从信号分离单元输出的第二频带信号的第二SAW滤波器和用于允许第二频带信号通过的高通滤波器，并且限制频带低于第二频率的信号的通过 高通滤波器位于将信号分离单元和第二SAW滤波器彼此连接的信号线上。

    Dry etching endpoint detection system
    12.
    发明授权
    Dry etching endpoint detection system 失效
    干蚀刻终点检测系统

    公开(公告)号：US06514375B2

    公开(公告)日：2003-02-04

    申请号：US09754768

    申请日：2001-01-04

    申请人： Masato Kijima

    发明人： Masato Kijima

    IPC分类号： G01N2100

    CPC分类号： H01J37/32935 ,  G01N21/68 ,  H01J37/32963

    摘要： A method and system for determining a dry etching endpoint, at which a dry etching process should be terminated. The dry etching process is carried out in a plasma etching system and comprises the steps of detecting an intensity of light emission generated in the dry etching process, the light emission being extracted through a window located on a side wall portion of a reaction chamber below a horizontal plane which is defined by a surface of a body to be etch treated. The detected intensity is compared to a predetermined threshold level.

    摘要翻译： 一种用于确定干蚀刻终点的方法和系统，其中应该终止干蚀刻工艺。 干蚀刻工艺在等离子体蚀刻系统中进行，包括以下步骤：检测在干法蚀刻工艺中产生的发光强度，发光通过位于反应室下侧的窗口 水平面由待蚀刻处理的物体的表面限定。 将检测到的强度与预定阈值水平进行比较。

    Highly rigid propylenic resin and blow molded article made therefrom
    13.
    发明授权
    Highly rigid propylenic resin and blow molded article made therefrom 失效
    高刚性丙烯树脂和由其制成的吹塑制品

    公开(公告)号：US5736613A

    公开(公告)日：1998-04-07

    申请号：US605133

    申请日：1996-03-13

    申请人： Masato Kijima ,  Masayuki Shinohara ,  Minoru Sugawara ,  Koki Hirano

    发明人： Masato Kijima ,  Masayuki Shinohara ,  Minoru Sugawara ,  Koki Hirano

    IPC分类号： B29C49/00 ,  C08F4/642 ,  C08F10/06 ,  C08F110/06 ,  C08F210/06 ,  C08F297/08

    CPC分类号： C08F10/06 ,  B29C49/0005 ,  B29K2023/12 ,  C08F110/06 ,  C08F210/06

    摘要： There are provided a highly rigid propylenic resin which has a melt index MI in the range of 0.1 to 1.2 g/10 minutes as determined at 230.degree. C. under 2.160 kg load and also satisfies a relationship between the MI and the elongational viscosity �Y(Pa.multidot.s)!, said relationship being represented by the expression 2.0.times.10.sup.5 .times.MI.sup.-0.68 .ltoreq.Y.ltoreq.8.0.times.10.sup.5 .times.MI.sup.-0.68 ; and a blow molded article made from the above resin. The propylenic resin has favorable resistance to draw down and can produce a large-sized and lightweight blow molded article excellent in rigidity, dimensional stability and heat resistance.

    摘要翻译： PCT No.PCT / JP95 / 01406 Sec。 371日期：1996年3月18日 102（e）1996年3月18日PCT提交1995年7月14日PCT公布。 公开号WO96 / 02381 日本1996年2月1日提供了一种高度刚性的丙烯树脂，其在230℃下在2.160kg负荷下的熔体指数MI在0.1至1.2g / 10分钟的范围内，并且还满足MI和 伸长粘度[Y（Paxs）]，所述关系由表达式为：××××××××××××××××××××××××××××××××××××××; 丙烯树脂具有良好的拉伸阻力，并且可以制造刚性，尺寸稳定性和耐热性优异的大型轻质的吹塑制品。

    Semiconductor device and method of manufacturing the same
    15.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07476947B2

    公开(公告)日：2009-01-13

    申请号：US11360288

    申请日：2006-02-22

    申请人： Naohiro Ueda ,  Masato Kijima

    发明人： Naohiro Ueda ,  Masato Kijima

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having a greater film thickness than the gate insulation film and formed adjacent to the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.

    摘要翻译： 公开了一种包括高击穿电压MOSFET的半导体器件。 MOSFET包括第二导电类型的源极区域和在第一导电类型的阱区域中形成的第二导电类型的漏极区域，形成在源极区域和漏极区域之间的沟道区域，栅极 形成在沟道区上的绝缘膜，与栅极绝缘膜相邻形成的膜厚度比栅极绝缘膜大的LOCOS氧化膜，以及形成在栅极绝缘膜和LOCOS氧化膜两侧的栅电极。

    Propylene copolymer and molded object obtained by molding the copolymer
    16.
    发明授权
    Propylene copolymer and molded object obtained by molding the copolymer 失效
    丙烯共聚物和通过模塑该共聚物获得的模制品

    公开(公告)号：US06423782B1

    公开(公告)日：2002-07-23

    申请号：US09719561

    申请日：2000-12-28

    申请人： Shinichi Yukimasa ,  Masahiko Endo ,  Masato Kijima ,  Takayuki Nakagawa

    发明人： Shinichi Yukimasa ,  Masahiko Endo ,  Masato Kijima ,  Takayuki Nakagawa

    IPC分类号： C08L2300

    CPC分类号： C08L23/10 ,  C08L23/14 ,  C08L23/142 ,  C08L2205/02 ,  C08L2666/04

    摘要： The invention relates to a propylene-based copolymer and its moldings which are transparent and have good ordinary impact resistance, good cold impact resistance, and well-balanced flexibility and blocking resistance. The propylene-based copolymer comprises from 50 to 90% by weight of a propylene-ethylene copolymer [A] of such that (1) its ethylene content (&agr;) falls between 0.2 and 10% by weight, (2) the amount of its fraction (Wp) eluted within the temperature range between (Tp−5)° C. and (Tp+5)° C. is at least 20% by weight, with Tp (°C.) being the peak temperature for essential elution in temperature-programmed fractionation chromatography of the copolymer, and (3) the amount of its fraction (W0) eluted within the temperature range not higher than 0° C. in temperature-programmed fractionation chromatography of the copolymer, and &agr; satisfy a relation of W0≦(3+2&agr;)/4, and from 10 to 50% by weight of a propylene-ethylene copolymer [B] having an ethylene content of from 10 to 25% by weight.

    摘要翻译： 本发明涉及一种丙烯类共聚物及其模塑品，它们是透明的，具有良好的耐冲击性，良好的耐冷冲击性和良好的平衡柔软性和抗粘连性。 基于丙烯的共聚物包含50至90重量％的丙烯 - 乙烯共聚物[A]，使得（1）其乙烯含量（α）为0.2至10重量％，（2）其量 在（Tp-5）℃和（Tp + 5）℃之间的温度范围内洗脱的级分（Wp）为至少20重量％，Tp（℃）为基本洗脱的峰值温度 共聚物的温度程序分级色谱法，和（3）在共聚物的温度程序分级色谱法中在不高于0℃的温度范围内洗脱的其级分（W0）的量，和α满足W0 <=（3 + 2alpha）/ 4，和10〜50重量％的乙烯含量为10〜25重量％的丙烯 - 乙烯共聚物[B]。

    Method for forming plural kinds of wells on a single semiconductor substrate
    19.
    发明授权
    Method for forming plural kinds of wells on a single semiconductor substrate 失效
    在单个半导体衬底上形成多种孔的方法

    公开(公告)号：US07504313B2

    公开(公告)日：2009-03-17

    申请号：US11367644

    申请日：2006-03-03

    申请人： Masato Kijima ,  Atsushi Harikai

    发明人： Masato Kijima ,  Atsushi Harikai

    IPC分类号： H01L21/76

    CPC分类号： H01L23/544 ,  H01L21/823892 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for forming plural kinds of wells on a single semiconductor substrate with an improved alignment accuracy and obviating the generation of step height between the wells. The method includes forming a selective etching film on the semiconductor substrate, forming openings on the selective etching film overlying a first well forming region and an alignment mark forming region using a first resist film as a mask for defining the first well forming region and the alignment mark forming region, implanting the first well forming region with a dopant of a first conductivity type and removing the first resist film, forming a second resist film to mask at least the first well forming region, having an opening overlying the alignment mark forming region larger than the opening of the selective etching film overlying the same region, and forming the alignment mark by performing an etching process using the second resist film and selective etching film as a mask.

    摘要翻译： 提供了一种用于在单个半导体衬底上形成多种孔的方法，其具有改进的对准精度并避免了在井之间产生台阶高度。 该方法包括在半导体衬底上形成选择性蚀刻膜，在第一阱形成区域上形成选择性蚀刻膜上的开口，使用第一抗蚀剂膜作为掩模形成对准标记形成区域，用于限定第一阱形成区域和对准 标记形成区域，用第一导电类型的掺杂剂注入第一阱形成区域并去除第一抗蚀剂膜，形成第二抗蚀剂膜以至少掩蔽第一阱形成区域，具有覆盖对准标记形成区域的开口较大 比通过相同区域上的选择性蚀刻膜的打开，并且通过使用第二抗蚀剂膜和选择性蚀刻膜作为掩模进行蚀刻工艺来形成对准标记。