公开(公告)号：US20080268626A1

公开(公告)日：2008-10-30

申请号：US12213676

申请日：2008-06-23

申请人： Masaaki Yoshida ,  Naohiro Ueda ,  Masato Kijima

发明人： Masaaki Yoshida ,  Naohiro Ueda ,  Masato Kijima

IPC分类号： H01L21/425

CPC分类号： H01L27/0928 ,  H01L21/823892 ,  H01L27/1052

摘要： A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.

公开(公告)号：US20060197150A1

公开(公告)日：2006-09-07

申请号：US11360288

申请日：2006-02-22

申请人： Naohiro Ueda ,  Masato Kijima

发明人： Naohiro Ueda ,  Masato Kijima

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having a greater film thickness than the gate insulation film and formed adjacent to the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.

公开(公告)号：US07476947B2

公开(公告)日：2009-01-13

申请号：US11360288

申请日：2006-02-22

申请人： Naohiro Ueda ,  Masato Kijima

发明人： Naohiro Ueda ,  Masato Kijima

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having a greater film thickness than the gate insulation film and formed adjacent to the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.

摘要翻译： 公开了一种包括高击穿电压MOSFET的半导体器件。 MOSFET包括第二导电类型的源极区域和在第一导电类型的阱区域中形成的第二导电类型的漏极区域，形成在源极区域和漏极区域之间的沟道区域，栅极 形成在沟道区上的绝缘膜，与栅极绝缘膜相邻形成的膜厚度比栅极绝缘膜大的LOCOS氧化膜，以及形成在栅极绝缘膜和LOCOS氧化膜两侧的栅电极。

公开(公告)号：US08003476B2

公开(公告)日：2011-08-23

申请号：US12213676

申请日：2008-06-23

申请人： Masaaki Yoshida ,  Naohiro Ueda ,  Masato Kijima

发明人： Masaaki Yoshida ,  Naohiro Ueda ,  Masato Kijima

IPC分类号： H01L21/331

CPC分类号： H01L27/0928 ,  H01L21/823892 ,  H01L27/1052

摘要： A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.

摘要翻译： 半导体装置具有以下构造，其中形成三个以上小的水平差的孔。 三类以上井中的一种井表面水平高于三类以上井中的其他类型井。 与其他种类的井中的至少一种井相邻并且自对准地形成一种井。 其他种类的阱在导电类型，杂质浓度和结深度之一不同，并且包括具有相同表面水平的至少两种阱。

公开(公告)号：US07871867B2

公开(公告)日：2011-01-18

申请号：US12271042

申请日：2008-11-14

申请人： Naohiro Ueda ,  Masato Kijima

发明人： Naohiro Ueda ,  Masato Kijima

IPC分类号： H01L21/332

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having greater film thickness than the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.

摘要翻译： 公开了一种包括高击穿电压MOSFET的半导体器件。 MOSFET包括第二导电类型的源极区域和在第一导电类型的阱区域中形成的第二导电类型的漏极区域，形成在源极区域和漏极区域之间的沟道区域，栅极 形成在沟道区上的绝缘膜，具有比栅极绝缘膜更大的膜厚度的LOCOS氧化物膜，以及跨越栅极绝缘膜和LOCOS氧化物膜的栅电极。

公开(公告)号：US07405460B2

公开(公告)日：2008-07-29

申请号：US10803931

申请日：2004-03-19

申请人： Masaaki Yoshida ,  Naohiro Ueda ,  Masato Kijima

发明人： Masaaki Yoshida ,  Naohiro Ueda ,  Masato Kijima

IPC分类号： H01L29/93

CPC分类号： H01L27/0928 ,  H01L21/823892 ,  H01L27/1052

摘要： A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.

摘要翻译： 半导体装置具有以下构造，其中形成三个以上小的水平差的孔。 三类以上井中的一种井表面水平高于三类以上井中的其他类型井。 与其他种类的井中的至少一种井相邻并且自对准地形成一种井。 其他种类的阱在导电类型，杂质浓度和结深度之一不同，并且包括具有相同表面水平的至少两种阱。

公开(公告)号：US07915655B2

公开(公告)日：2011-03-29

申请号：US12056603

申请日：2008-03-27

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H01L27/108

CPC分类号： H01L21/823418 ,  H01L27/088 ,  H01L29/42324 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a semiconductor substrate and a metal-oxide semiconductor transistor. A first dielectric layer of the metal oxide semiconductor transistor overlaps source and drain electrodes and a channel region of the transistor. A first drain region is away from the channel region and the first dielectric layer. A second drain region is between the first drain region and the channel region. A gate electrode is on the first dielectric layer and connected to a gate wire, and includes first and second gate layers and a dielectric layer therebetween. The first gate layer has one edge laterally spaced from the first drain region and resting over the second drain region, and is isolated from the gate wire. The second gate layer is over the first gate layer and is connected to the gate wire.

摘要翻译： 半导体器件包括半导体衬底和金属氧化物半导体晶体管。 金属氧化物半导体晶体管的第一电介质层与源极和漏极以及晶体管的沟道区重叠。 第一漏极区域远离沟道区域和第一介电层。 第二漏区在第一漏区和沟道区之间。 栅电极位于第一电介质层上并连接到栅极线，并且包括第一和第二栅极层和介电层之间。 第一栅极层具有与第一漏极区域横向间隔开并且搁置在第二漏极区域上的一个边缘，并且与栅极线隔离。 第二栅极层在第一栅极层上方并且连接到栅极线。

公开(公告)号：US07755195B2

公开(公告)日：2010-07-13

申请号：US11517781

申请日：2006-09-08

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/45099

摘要： A semiconductor apparatus includes a device, two metal-wiring layers, and an insulation film. The device includes first and second electrodes. The two metal-wiring layers include uppermost and next-uppermost metal-wiring layers. The insulation film is formed on the uppermost metal-wiring layer and includes first and second pad openings. The uppermost metal-wiring layer has a first portion exposed to air through the first pad opening and forming a first electrode pad, and the uppermost metal-wiring layer has a second portion exposed to air through the second pad opening and forming a second electrode pad. The first and second electrode pads are located over the device and are electrically connected to the first and second electrodes, respectively. The next-uppermost metal-wiring layer has a first portion located under the first electrode pad and electrically connected thereto, and a second portion located under the second electrode pad and electrically connected thereto.

摘要翻译： 半导体装置包括器件，两个金属布线层和绝缘膜。 该装置包括第一和第二电极。 两个金属布线层包括最上面和下一个最上层的金属布线层。 绝缘膜形成在最上层的金属布线层上，并且包括第一和第二焊盘开口。 最上面的金属布线层具有通过第一焊盘开口暴露于空气的第一部分，并形成第一电极焊盘，最上面的金属布线层具有通过第二焊盘开口暴露于空气的第二部分，并形成第二电极焊盘 。 第一和第二电极焊盘位于器件上方并分别与第一和第二电极电连接。 下一个最上层的金属布线层具有位于第一电极焊盘下方并与之电连接的第一部分，以及位于第二电极焊盘下方并与之电连接的第二部分。

公开(公告)号：US07084035B2

公开(公告)日：2006-08-01

申请号：US11104433

申请日：2005-04-13

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629 ,  H01L21/82345 ,  H01L21/823462 ,  Y10S438/981

摘要： A method for forming three kinds of MOS transistors on a single semiconductor substrate, each provided with gate oxides different in thickness from each other, without detracting from the device characteristics. The method includes the steps of forming a dielectric layer for device isolation for defining first, second, and third regions, and buffer oxide layers on the surface of a semiconductor substrate; after forming an oxidation resistance layer, which has an opening for exposing the first region, performing a first thermal oxidation process for forming a first gate oxide layer overlaying the first region; forming a first gate electrode on the first gate oxide layer; removing the buffer oxide layer overlying the third region, having an opening for exposing the third region; performing a second thermal oxidation process for forming a second gate oxide layer, having a thickness different from the first gate oxide, and for forming a third gate oxide layer having a thickness different from the first, and the second gate oxides.

摘要翻译： 一种用于在单个半导体衬底上形成三种MOS晶体管的方法，每个半导体衬底均设置有彼此不同厚度的栅极氧化物，而不会降低器件特性。 该方法包括以下步骤：在半导体衬底的表面上形成用于器件隔离的介电层，用于限定第一，第二和第三区域以及缓冲氧化物层; 在形成具有用于暴露第一区域的开口的抗氧化层之后，进行用于形成覆盖第一区域的第一栅极氧化物层的第一热氧化工艺; 在所述第一栅极氧化物层上形成第一栅电极; 去除覆盖在第三区域上的缓冲氧化物层，具有用于暴露第三区域的开口; 进行第二热氧化工艺以形成具有不同于第一栅极氧化物的厚度的第二栅极氧化物层，以及用于形成具有不同于第一栅极氧化物的厚度的第三栅极氧化物层。

公开(公告)号：US06917081B2

公开(公告)日：2005-07-12

申请号：US10422786

申请日：2003-04-25

申请人： Naohiro Ueda ,  Yoshinori Ueda

发明人： Naohiro Ueda ,  Yoshinori Ueda

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/0928

摘要： A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an offset Pch transistor including P-type source and drain each formed in an N-well spatially separated from one another, and the drain surrounded by a low concentration P-type diffusion layer; a triple well including a deep N-well, and a P-type IP well formed therein; a normal N-well for forming a Pch MOS transistor; and a normal P-well for forming an Nch MOS transistor; in which simultaneously formed are the low concentration N-type diffusion layer, N-well and normal N-well; the P-well and normal P-well; and the low concentration P-type diffusion layer and IP well.

摘要翻译： 提供了一种半导体器件，其包括形成在同一衬底中的若干器件组件，例如具有偏置N沟道晶体管的P衬底，其中N型晶体管包括N型源极和漏极，其各自形成在彼此空间上分离的P阱中，并且漏极包围 通过低浓度N型扩散层; 偏移Pch晶体管，包括P型源极和漏极，各自形成在空间上彼此分离的N阱中，并且由低浓度P型扩散层包围的漏极; 包括深N阱的三阱和在其中形成的P型IP阱; 用于形成Pch MOS晶体管的正常N阱; 以及用于形成Nch MOS晶体管的正常P阱; 其中同时形成低浓度N型扩散层，N阱和正常N阱; P井和正常P井; 和低浓度P型扩散层和IP井。