公开(公告)号：US08622677B2

公开(公告)日：2014-01-07

申请号：US12744153

申请日：2008-05-23

申请人： Zhiqiang Wu ,  Shaofan Zeng ,  Xiangyong Zhong

发明人： Zhiqiang Wu ,  Shaofan Zeng ,  Xiangyong Zhong

IPC分类号： F16B37/00

CPC分类号： B60S9/08

摘要： A semi-trailer leg loading nut includes a screwed hole provided on a nut column and connecting two ends of the nut. Said nut is a two-layered structure formed of a top layer and an under layer or a three-layered structure formed of a top layer, an intermediate layer and an under layer. The outer outline of at least two layers of the nut is a square with the same cutting angle. The side length of the two layers of squares is equal. The outer outline projection of the two layers of squares overlap with each other along the column axis direction. The outer outline projection of the other layer is within the overlapped projection of the two layers along the column axis direction. A funneled oil cup or an oil groove is provided on the top layer of the nut and communicates with the screwed hole. A bottom of the under layer of the nut is plane and is pressed on a loading plate in a quadrate pipe to transfer load.

摘要翻译： 半挂车小腿装载螺母包括设在螺母柱上并连接螺母两端的螺纹孔。 所述螺母是由顶层和下层或由顶层，中间层和下层形成的三层结构形成的两层结构。 螺母的至少两层的外轮廓是具有相同切割角度的正方形。 两层正方形的边长相等。 两层正方形的外轮廓投影沿柱轴方向相互重叠。 另一层的外轮廓投影在两列沿着列轴方向的重叠投影内。 漏斗油杯或油槽设置在螺母的顶层上，并与螺纹孔连通。 螺母底层的底部是平面的，并被压在方管中的装载板上以传递负载。

公开(公告)号：US20120056398A1

公开(公告)日：2012-03-08

申请号：US13320543

申请日：2009-12-01

申请人： Zhiqiang Wu

发明人： Zhiqiang Wu

IPC分类号： B60G11/27 ,  B60G9/00

CPC分类号： B60G9/003 ,  B60G2202/152 ,  B60G2204/4306 ,  B60G2206/30

摘要： A semi-trailer axle and suspension connecting structure includes an axle (5), a suspension system and a connecting member arranged on the axle (5) body and a suspension support plate (6) of the suspension system. A locating structure is arranged on the match surface of the axle (5) and the suspension support plate (6) to prevent the circumferentially and axially relative displacement between the axle (5) and the suspension support plate (6). The invention omits a welding process for the axle body and the suspension support plate (6). The axle body still keeps a good strength structure while the firm connection of the axle body and the suspension arrives, and the stress damage caused by welding is avoided.

摘要翻译： 半挂车轴和悬挂连接结构包括轴（5），悬架系统和布置在轴（5）主体上的连接构件和悬架系统的悬架支撑板（6）。 定位结构布置在轴（5）和悬架支撑板（6）的匹配表面上，以防止轴（5）和悬架支撑板（6）之间的周向和轴向相对位移。 本发明省略了用于车轴和悬架支撑板（6）的焊接工艺。 轴体和悬架的牢固连接到达时，轴体仍保持良好的强度结构，避免了焊接引起的应力损伤。

公开(公告)号：US20110070703A1

公开(公告)日：2011-03-24

申请号：US12549862

申请日：2009-08-28

申请人： Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

发明人： Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).

摘要翻译： 一种用于使用应力存储技术（SMT）层（126）形成NMOS晶体管（104）和嵌入式SiGe（eSiGe）PMOS晶体管（102）的集成工艺流程。 SMT层（126）沉积在NMOS晶体管（104）和PMOS晶体管（102）两者之上。 在PMOS晶体管（102）上方的SMT层（126）的部分被各向异性蚀刻以形成间隔物（128），而不通过NMOS晶体管（104）蚀刻SMT层（126）的部分。 间隔物（128）用于对准SiGe凹陷蚀刻和生长以形成SiGe源极/漏极区域（132）。 在蚀刻SMT层（126）之后执行源极/漏极退火，使得SMT层（126）在不降低PMOS晶体管（102）的情况下向NMOS晶体管（104）提供期望的应力。

公开(公告)号：US07189602B2

公开(公告)日：2007-03-13

申请号：US09998165

申请日：2001-12-03

申请人： Tongbi Jiang ,  Zhiqiang Wu

发明人： Tongbi Jiang ,  Zhiqiang Wu

IPC分类号： H01L21/00

CPC分类号： H01L24/06 ,  H01L23/4827 ,  H01L23/4828 ,  H01L23/585 ,  H01L24/48 ,  H01L27/08 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2223/665 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/8546 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform bias voltage over the substrate. The conductive layer can also be used to apply a bias voltage to the substrate and reduce the number of bias voltage distribution regions required.

摘要翻译： 半导体器件设置有设置在半导体衬底的背面上的导电层。 导电层有助于在衬底上保持均匀的偏置电压。 导电层也可用于向衬底施加偏置电压并减少所需的偏置电压分布区域的数量。

公开(公告)号：US07118979B2

公开(公告)日：2006-10-10

申请号：US10701818

申请日：2003-11-05

申请人： Kaiping Liu ,  Zhiqiang Wu ,  Majid Movahed Mansoorz

发明人： Kaiping Liu ,  Zhiqiang Wu ,  Majid Movahed Mansoorz

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/823828

摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

摘要翻译： 本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。 在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。 晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

公开(公告)号：US06875650B2

公开(公告)日：2005-04-05

申请号：US10684948

申请日：2003-10-14

申请人： Craig T. Salling ,  Zhiqiang Wu

发明人： Craig T. Salling ,  Zhiqiang Wu

IPC分类号： H01L27/04 ,  H01L21/761 ,  H01L21/822 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L29/1083 ,  H01L21/761 ,  H01L29/7833

摘要： On the surface of a semiconductor material of a first conductivity type 101a, a lateral MOS transistor 100 is described surrounded by a well 171 of the opposite conductivity type and, nested within the well, an electrical isolation region 102. The semiconductor region 101a embedding this transistor has a resistivity higher than the remainder of the semiconductor material 101 and further contains a buried layer 160 of the opposite conductivity type. This layer 160 extends laterally to the wells 171, thereby electrically isolating the near-surface portion of the semiconductor region from the remainder of the semiconductor material, and enabling the MOS transistor to operate as an electrically isolated high-voltage I/O transistor for circuit noise reduction, while having low drain junction capacitance.In the first embodiment of the invention (FIG. 1), the buried layer 171 extends vertically deeper from the surface than the electrical isolation region 102, thereby enabling a separate contact 106 to the electrically isolated near-surface portion 101a of the semiconductor region.

摘要翻译： 在第一导电类型101a的半导体材料的表面上，横向MOS晶体管100被描述为由相反导电类型的阱171包围，并且嵌套在阱内的电隔离区域102.半导体区域101a嵌入该 晶体管的电阻率高于半导体材料101的其余部分，并且还包含相反导电类型的掩埋层160。 该层160横向延伸到阱171，从而将半导体区域的近表面部分与半导体材料的其余部分电绝缘，并且使MOS晶体管能够作为用于电路的电隔离的高压I / O晶体管工作 噪声降低，同时具有低漏极结电容。在本发明的第一实施例（图1）中，掩埋层171从表面比电隔离区域102垂直地更深地延伸，从而使单独的触点106能够电隔离 半导体区域的近表面部分101a。

公开(公告)号：US20050030697A1

公开(公告)日：2005-02-10

申请号：US10932503

申请日：2004-09-02

申请人： Zhiqiang Wu ,  Kunal Parekh ,  Li Li

发明人： Zhiqiang Wu ,  Kunal Parekh ,  Li Li

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01G4/30

CPC分类号： H01L27/10852 ,  H01L28/82

摘要： A capacitor is formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

摘要翻译： 电容器形成为具有大致凹入的形状并且具有可选的折叠或回旋表面。 凹形形状在小体积内优化表面积，从而使电容器能够保持大量电荷，从而有助于微电子领域中的增加的小型化努力。 电容器以与电致密DRAM阵列一致的微电子方式制造。 制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

公开(公告)号：US06820502B2

公开(公告)日：2004-11-23

申请号：US10366822

申请日：2003-02-14

申请人： Tongbi Jiang ,  Zhiqiang Wu

发明人： Tongbi Jiang ,  Zhiqiang Wu

IPC分类号： G01L516

CPC分类号： G01L1/205

摘要： A high-resolution pressure-sensing device is disclosed. The device includes an insulating flexible matrix having a plurality of filler particles. Application of a force to the matrix causes compression of the matrix. This results in the filler particles occupying a greater amount of space within the matrix relative to when no force is applied. A detector attached to the matrix detects or measures the volume of the filler particles relative to the volume of the matrix, and therefore determines the force applied to the matrix. Preferably, the resistivity of the matrix is inversely proportional to the volume percent of the filler particles, in which case the detector is a resistance-measuring circuit.

摘要翻译： 公开了一种高分辨率压力感测装置。 该装置包括具有多个填料颗粒的绝缘柔性基质。 对矩阵施加力会导致矩阵的压缩。 这导致在没有施加力的情况下，填料颗粒在基质内占据更大量的空间。 连接到基体的检测器检测或测量填料颗粒相对于基体体积的体积，因此确定施加到基质上的力。 优选地，基质的电阻率与填料颗粒的体积百分比成反比，在这种情况下，检测器是电阻测量电路。

公开(公告)号：US06740923B2

公开(公告)日：2004-05-25

申请号：US10145250

申请日：2002-05-14

申请人： Zhiqiang Wu ,  Kunal Parekh ,  Li Li

发明人： Zhiqiang Wu ,  Kunal Parekh ,  Li Li

IPC分类号： H01L31119

CPC分类号： H01L27/10852 ,  H01L28/82

摘要： The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

摘要翻译： 本发明涉及一种电容器的制造，该电容器形成为具有大致凹入形状且具有可选择的折叠或回旋表面。 凹形形状在小体积内优化表面积，从而使电容器能够保持大量电荷，从而有助于微电子领域中的增加的小型化努力。 电容器以与电致密DRAM阵列一致的微电子方式制造。 制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

公开(公告)号：US06727131B2

公开(公告)日：2004-04-27

申请号：US10279650

申请日：2002-10-24

申请人： Zhiqiang Wu ,  Kaiping Liu

发明人： Zhiqiang Wu ,  Kaiping Liu

IPC分类号： H01L218238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L29/6659

摘要： A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor defines a channel region disposed inwardly from the gate conductor. Source and drain regions are formed in the semiconductor substrate, each disposed adjacent one edge of the channel region. The semiconductor substrate and the source and drain regions have an associated bottom wall junction capacitance. A transient enhanced diffusion anneal is used to affect ion concentration profiles associated with the source and drain regions, resulting in an increased balance in the ion concentration profiles of the source and drain regions and an ion concentration associated with the semiconductor substrate, which results in reduction of the bottom wall junction capacitance.

摘要翻译： 提供一种形成半导体器件的方法，其包括形成靠近并与半导体衬底的外表面绝缘的栅极导体。 栅极导体限定了从栅极导体向内设置的沟道区。 源极和漏极区域形成在半导体衬底中，每个设置在沟道区域的一个边缘附近。 半导体衬底和源极和漏极区域具有相关联的底壁结电容。 使用瞬时增强扩散退火来影响与源区和漏区相关的离子浓度分布，导致源区和漏区的离子浓度分布的增加平衡以及与半导体衬底相关联的离子浓度，这导致减少 的底壁结电容。