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公开(公告)号：US10250199B2
公开(公告)日：2019-04-02
申请号：US15268229
申请日：2016-09-16
Applicant: pSemi Corporation
Inventor： Jonathan Klaren , Poojan Wagh , David Kovac , Eric S. Shapiro , Neil Calanca , Dan William Nobbe , Christopher Murphy , Robert Mark Englekirk , Emre Ayranci , Keith Bargroff , Tero Tapio Ranta
Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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公开(公告)号：US10027283B2
公开(公告)日：2018-07-17
申请号：US15258806
申请日：2016-09-07
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Arun Srikanth Peri
Abstract: Various methods and circuital arrangements for controlling an RF amplifier while reducing size, cost and power consumption are presented. Included is an amplifier controller unit that provides different current amplification stages that can be used for calibrating an output power of the RF amplifier based on a reference current. Order of the current amplification stages starting from the reference current allow reduction in size, cost and power consumption.
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公开(公告)号：US20250158572A1
公开(公告)日：2025-05-15
申请号：US19026181
申请日：2025-01-16
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号：US20240039479A1
公开(公告)日：2024-02-01
申请号：US18447207
申请日：2023-08-09
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
CPC classification number: H03F1/0211 , H03F3/193 , H03F1/0261 , H03F1/223 , H03F2200/451 , H03F2200/21 , H03F2200/18 , H03F2200/522
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US20230396217A1
公开(公告)日：2023-12-07
申请号：US18328987
申请日：2023-06-05
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
CPC classification number: H03F1/0227 , H03F1/56 , H03F3/193 , H03F1/223 , H03F1/301 , H03F3/189 , H03F2200/18 , H03F2200/453 , H03F2200/249
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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Patent Agency Ranking
公开(公告)号：US20220158589A1
公开(公告)日：2022-05-19
申请号：US17531510
申请日：2021-11-19
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US10819288B2
公开(公告)日：2020-10-27
申请号：US16283298
申请日：2019-02-22
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号：US11984852B2
公开(公告)日：2024-05-14
申请号：US18328987
申请日：2023-06-05
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
CPC classification number: H03F1/0227 , H03F1/223 , H03F1/301 , H03F1/56 , H03F3/189 , H03F3/193 , H03F2200/18 , H03F2200/249 , H03F2200/453
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号：US20230081055A1
公开(公告)日：2023-03-16
申请号：US17950708
申请日：2022-09-22
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号：US11456705B2
公开(公告)日：2022-09-27
申请号：US17074070
申请日：2020-10-19
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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