公开(公告)号：US10855437B1

公开(公告)日：2020-12-01

申请号：US16583234

申请日：2019-09-25

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Ling Chen ,  Andrew Chao ,  Xiao-Dong Fei ,  Wei Liu

IPC: H04L7/033 ,  H03L7/08

Abstract: The present invention provides a clock data recovery apparatus and an operation method thereof. The clock data recovery apparatus includes an equalizer, a phase detector, a charge pump, and an oscillation circuit. The equalizer is configured to equalize raw data to generate equalized data. The phase detector is coupled to the equalizer to receive the equalized data. The phase detector is configured to generate a detection result according to the equalized data. The phase detector performs pattern-filtering on the equalized data to filter out at least one pattern. The charge pump is coupled to the phase detector to receive the detection result. The charge pump is configured to generate a control signal according to the detection result. The oscillation circuit is coupled to the charge pump to receive the control signal. The oscillation circuit is configured to generate a clock signal according to the control signal.

公开(公告)号：US10833674B2

公开(公告)日：2020-11-10

申请号：US16554652

申请日：2019-08-29

Applicant: Faraday Technology Corp.

Inventor： Feng Xu ,  Shu Dong Wu ,  Zhen Liang Zhang

IPC: H03K17/687 ,  H03K19/20 ,  H03M1/12

Abstract: A switch device including a switch circuit and switch controller. The switch circuit comprises first and second switches to selectively enable a path between an input terminal and an output terminal. The switch controller refers to a selection signal and a switch signal to respectively generate a first switch control signal at a first switch control signal output terminal and a second switch control signal at a second switch control signal output terminal. When the voltage level of an input signal at the input terminal is larger than a power voltage, the switch controller generates the first switch control signal and the second switch control signal capable of turning off the switch circuit. When the voltage level of the input signal is not larger than the power voltage, the switch controller generates the first switch control signal and the second switch control signal according to the switch signal.

公开(公告)号：US10749508B1

公开(公告)日：2020-08-18

申请号：US16525686

申请日：2019-07-30

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar Jain

IPC: H03K5/04 ,  H03K3/017 ,  H03K3/356

Abstract: A signal converter, a duty-cycle corrector, and a differential clock generator are provided. The differential clock generator includes the signal converter and the duty-cycle corrector. The signal converter is capable of calibrating skew distortion, and the duty-cycle corrector is capable of calibrating duty-cycle distortion. With the signal converter and the duty-cycle corrector, the differential clock generator can be applied to communication devices operating at high frequency.

公开(公告)号：US09971369B1

公开(公告)日：2018-05-15

申请号：US15496129

申请日：2017-04-25

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chi-Yang Chen ,  Wen-Chi Huang

IPC: G05F1/46

CPC classification number: G05F1/468

Abstract: A voltage regulator is connected with an input/output circuit. The voltage regulator includes a controlling circuit, a sink voltage generator and a source voltage generator. The controlling circuit generates a first reference voltage, a second reference voltage, a first power start control signal and a second power start control signal. The sink voltage generator receives the first reference voltage and the first power start control signal. The source voltage generator receives the second reference voltage and the second power start control signal. When the voltage regulator is in a normal working state, the controlling circuit inactivates the first power start control signal and the second power start control signal, the sink voltage generator generates a sink voltage according to the first reference voltage, and the source voltage generator generates a source voltage according to the second reference voltage.

公开(公告)号：US09641159B1

公开(公告)日：2017-05-02

申请号：US15046451

申请日：2016-02-18

Applicant: Faraday Technology Corp.

Inventor： Chiang-Hsiang Liao ,  Sheng-Hua Chen

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/0372 ,  H03K3/3562

Abstract: A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.

公开(公告)号：US20160373060A1

公开(公告)日：2016-12-22

申请号：US14856571

申请日：2015-09-17

Applicant: Wei-Chieh Liao ,  Chi-Sheng Liao

Inventor： Wei-Chieh Liao ,  Chi-Sheng Liao

IPC: H03B5/36 ,  G06F17/50

CPC classification number: H03B5/364 ,  G06F17/5036 ,  G06F17/5063

Abstract: A crystal oscillation circuit, a gain stage of the crystal oscillation circuit and a method for designing the same are provided. The gain stage includes multiple amplifiers and multiple current-limiting resistors. Input terminals of the amplifiers are coupled together to a first bonding pad, wherein transconductances of the amplifiers are different from each other. The first bonding pad is used for electrically coupling to a first terminal of an oscillation crystal module. First terminals of the current-limiting resistors are respectively coupled to output terminals of the amplifiers in a one-on-one manner, and second terminals of the current-limiting resistors are coupled together to a second bonding pad, wherein the second bonding pad is used for electrically coupling to a second terminal of the oscillation crystal module.

Abstract translation: 提供晶体振荡电路，晶体振荡电路的增益级及其设计方法。 增益级包括多个放大器和多个限流电阻。 放大器的输入端子耦合到第一接合焊盘，其中放大器的跨导彼此不同。 第一焊盘用于电耦合到振荡晶体模块的第一端子。 限流电阻器的第一端子分别以一对一的方式耦合到放大器的输出端子，并且限流电阻器的第二端子耦合到第二接合焊盘，其中第二接合焊盘是 用于电耦合到振荡晶体模块的第二端子。

公开(公告)号：US09466357B2

公开(公告)日：2016-10-11

申请号：US14602739

申请日：2015-01-22

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Ching-Te Chuang ,  Chien-Yu Lu ,  Ming-Ching Zheng ,  Ming-Hsien Tu

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/16 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.

Abstract translation: 提供了一种用于减轻包括第一和第二放电控制路径的写干扰的电路并将其应用于双端口SRAM。 第一放电控制路径连接到第二端口和第一端口的位线，以及第一控制线。 第二放电控制路径连接到第二端口和第一端口与第一控制线的反位线。 当第二端口和第一端口的位线分别处于高电平电压和低电平电压，并且第一控制线路工作时，产生第一放电电流。 当第二端口和第一端口的反位线分别处于高电平电压和低电平电压，并且第一控制线工作时，产生第二放电电流。

公开(公告)号：US09385733B2

公开(公告)日：2016-07-05

申请号：US14527779

申请日：2014-10-30

Applicant: Faraday Technology Corp.

Inventor： Chia-Liang Lai ,  Song-Rong Han ,  Jung-Yu Chang ,  Wei-Ming Lin

IPC: H03L7/197 ,  H03K23/68

CPC classification number: H03L7/1976 ,  H03K21/023 ,  H03K23/68 ,  H03L7/1974

Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Abstract translation: 提供时钟发生装置及其分数分频器。 分数分频器包括分频器（FD），多个采样器，选择器和控制电路。 FD的输入端耦合到多相频率发生电路的输出端。 采样器的输入端耦合到FD的输出端。 采样器的触发端接收采样时钟信号。 选择器的输入端耦合到采样器的输出端。 选择器的输出端耦合到多相频率发生电路的反馈端。 控制电路向选择器的控制端提供分数代码，以便控制选择器选择性地将一个采样器的输出端耦合到多相频率发生电路的反馈端。

公开(公告)号：US20150271459A1

公开(公告)日：2015-09-24

申请号：US14276974

申请日：2014-05-13

Applicant: Hung-Chang Chuang

Inventor： Hung-Chang Chuang

IPC: H04N9/64 ,  G06K9/46 ,  G06K9/52 ,  G06T7/40

CPC classification number: H04N9/646 ,  G06K9/03 ,  G06K9/4642 ,  G06K9/4652 ,  G06K9/52 ,  G06T5/009 ,  G06T2207/10024 ,  H04N1/58 ,  H04N1/6041 ,  H04N9/67

Abstract: An image sensing apparatus, a color-correction matrix correcting method and a look-up table establishing method are provided. The image sensing apparatus calculates a block statistics value corresponding to a block of pixels in an image sensor array. Based on a look-up table, the image sensing apparatus determines a covariance value corresponding to a current gain value. According to the covariance value and the block statistics value, the image sensing apparatus corrects a color-correction matrix corresponding to the block of pixels. The image sensing apparatus can use an amended color-correction matrix to correct the color of the pixel, so as to reduce chroma noise or other noise.

Abstract translation: 提供了一种图像感测装置，色彩校正矩阵校正方法和查找表建立方法。 图像感测装置计算与图像传感器阵列中的像素块对应的块统计值。 基于查找表，图像感测装置确定与当前增益值对应的协方差值。 根据协方差值和块统计值，图像检测装置校正与像素块对应的颜色校正矩阵。 图像感测装置可以使用修正的颜色校正矩阵来校正像素的颜色，以便降低色度噪声或其他噪声。

公开(公告)号：US20150189182A1

公开(公告)日：2015-07-02

申请号：US14219012

申请日：2014-03-19

Applicant: Hsiu-Wei Ho ,  Ho-Yi Chiang

Inventor： Hsiu-Wei Ho ,  Ho-Yi Chiang

IPC: H04N5/232

CPC classification number: H04N5/23267 ,  G06T5/002 ,  G06T5/40 ,  G06T7/231 ,  G06T2207/10016 ,  G06T2207/20016 ,  G06T2207/20021 ,  G06T2207/20076 ,  H04N5/23254

Abstract: A method for reducing the jitters of video frames is provided, which includes the steps of dividing a frame into multiple blocks, selecting at least one block according to a variance of each block, determining a global motion vector of the frame in a direction according to the selected block(s), and performing motion compensation on the frame in the direction according to the global motion vector.

Abstract translation: 提供了一种减少视频帧抖动的方法，包括以下步骤：将帧划分成多个块，根据每个块的方差来选择至少一个块;根据帧的方向确定帧的全局运动矢量; 所选择的块，并且在根据全局运动矢量的方向上对帧执行运动补偿。