公开(公告)号：US20250159877A1

公开(公告)日：2025-05-15

申请号：US19022523

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H10B41/30 ,  H01L21/768 ,  H10B41/20 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20250158618A1

公开(公告)日：2025-05-15

申请号：US19023071

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer

IPC: H03K19/17756 ,  G11C16/04 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17764 ,  H10B41/40 ,  H10B63/00 ,  H10D88/00

Abstract: A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.

公开(公告)号：US20250157926A1

公开(公告)日：2025-05-15

申请号：US19025392

申请日：2025-01-16

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron S. Yip

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US20250157828A1

公开(公告)日：2025-05-15

申请号：US18896782

申请日：2024-09-25

Applicant: Micron Technology, Inc.

Inventor： Youngrae Kim ,  Ying-Ta Chiu ,  Wei Hung Tang

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate and a stack of semiconductor devices. The stack of semiconductor devices includes core semiconductor devices and a top semiconductor device disposed at the top of the stack. Each core device has a first thickness. The top device has a second thickness that is greater than the first thickness. Every device in the stack has a gap beneath it, with underfill material filling every gap and covering the sides of the core semiconductor devices. The underfill material has a squeeze-out region protruding away from the stack a first distance, and a squeeze-up region extending up the top semiconductor device a second distance. The second distance measures at least the same as the height of the gap beneath the devices in the stack.

公开(公告)号：US20250156351A1

公开(公告)日：2025-05-15

申请号：US18908554

申请日：2024-10-07

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon

IPC: G06F13/18 ,  G06F13/16

Abstract: A memory module control hub includes a first priority logic circuit configured to receive an in-band interrupt (IBI) message from a memory device having a unique identifier and configured to set a first priority flag based on a category of the IBI message, and a second priority logic circuit configured to receive the IBI message from the memory device and configured to set a second priority flag based on the category of the IBI message. The memory module control hub further includes a dynamic identifier assignment circuit configured to adjust priority bits of the unique identifier based on whether the first or second priority flags are set.

公开(公告)号：US20250156296A1

公开(公告)日：2025-05-15

申请号：US18929369

申请日：2024-10-28

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Nicola Colella ,  Rakeshkumar Dayabhai Vaghasiya ,  Deping He

IPC: G06F11/34 ,  G06F9/50

Abstract: Methods, systems, and devices for memory allocation for a benchmark test are described. A memory system may be configured to allocate and deallocate portions of a volatile memory for specific uses based on detecting the occurrence of a benchmark testing operation. For example, the memory system may be configured to detect the occurrence of a benchmark testing operation based on the occurrence of one or more conditions. After detecting the benchmark testing operation, the memory system may deallocate a portion of the volatile memory associated with multiple-level cell accesses and may allocate (e.g., reallocate) the portion for storing additional logical-to-physical mappings.

公开(公告)号：US20250156251A1

公开(公告)日：2025-05-15

申请号：US19022854

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Paul Dlugosch

IPC: G06F9/54 ,  G06F11/30 ,  G06F11/34 ,  G06F15/173 ,  G06F15/82 ,  G06N5/02

Abstract: Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.

公开(公告)号：US20250156123A1

公开(公告)日：2025-05-15

申请号：US19020825

申请日：2025-01-14

Applicant: Micron Technology, Inc.

Inventor： Yun Li ,  Jiangang Wu ,  James P. Crowley

IPC: G06F3/06

Abstract: Methods, systems, and devices for a read counter for quality of service design are described. First commands may be assigned to a first queue of a memory die of a memory sub-system, wherein the first queue is associated with a first priority level. The memory die may include a second queue associated with a second priority level different from the first priority level, the second queue comprising one or more second commands assigned. Based at least in part on a counter associated with the first queue and the first and second priority levels, it may be determined that a threshold number of the first commands of the first queue have issued without a command from the one or more second commands having issued. A command from the second commands may issue before issuing a next command of the first commands based at least in part on the counter.

公开(公告)号：US20250156098A1

公开(公告)日：2025-05-15

申请号：US19022852

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: Disclosed in some examples, are methods, systems, devices, and machine readable mediums that store instructions for programmable atomic transactions in a memory of the programmable atomic unit prior to execution of the programmable atomic transaction. The memory in some examples may be an instruction RAM. The memory in some examples may be partitioned into partitions of a fixed size that stores a same number of instructions. Each programmable atomic transaction may use one or more contiguously located instruction partitions. By loading the instructions ahead of time, the instructions are ready for execution when the transaction is requested.

公开(公告)号：US20250156092A1

公开(公告)日：2025-05-15

申请号：US19022888

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Haojie Ye

IPC: G06F3/06

Abstract: Disclosed in some examples are systems, devices, machine-readable mediums, and methods for customizing an in-memory versioning mode for each memory location according to a predicted access behavior to optimize memory device performance. Usage data in a previous time period may be utilized along with policy rules to determine whether to configure a particular memory address as a zero copy or direct copy mode. For example, memory addresses that are read frequently may be configured as direct copy mode to reduce the read latency penalty. This improves the functioning of the memory system by reducing read latency for memory addresses that are frequently read but written to less frequently, and reduces write latency for memory locations that are frequently written to, but not read as frequently.