公开(公告)号：US20250036304A1

公开(公告)日：2025-01-30

申请号：US18786883

申请日：2024-07-29

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Dongyun Lee

IPC: G06F3/06

Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.

公开(公告)号：US20250028636A1

公开(公告)日：2025-01-23

申请号：US18794937

申请日：2024-08-05

Applicant: Rambus Inc.

Inventor： Taeksang SONG ,  Steven C. WOO ,  Torsten PARTSCH

IPC: G06F12/06 ,  G11C11/408

Abstract: Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

公开(公告)号：US12205669B2

公开(公告)日：2025-01-21

申请号：US18513473

申请日：2023-11-17

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  David Wang

IPC: G11C7/10 ,  G06F11/07 ,  G06F11/10 ,  G11C5/04 ,  G11C29/04 ,  G11C29/52

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US12204469B2

公开(公告)日：2025-01-21

申请号：US18586867

申请日：2024-02-26

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Haukness

IPC: G06F13/16 ,  G06F5/14

Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

公开(公告)号：US12204446B2

公开(公告)日：2025-01-21

申请号：US18140441

申请日：2023-04-27

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood

IPC: G06F12/02 ,  G06F12/0891

Abstract: A buffer/interface device of a memory node reads a block of data (e.g., page). As each unit of data (e.g., cache line sized) of the block is read, it is compared against one or more predefined patterns (e.g., all 0's, all 1's, etc.). If the block (page) is only storing one of the predefined patterns, a flag in the page table entry for the block is set to indicate the block is only storing one of the predefined patterns. The physical memory the block was occupying may then be deallocated so other data may be stored using those physical memory addresses.

公开(公告)号：US20250021497A1

公开(公告)日：2025-01-16

申请号：US18794704

申请日：2024-08-05

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F13/16 ,  G06F11/07 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F13/40

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US20250004867A1

公开(公告)日：2025-01-02

申请号：US18670952

申请日：2024-05-22

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/00 ,  H04L1/08 ,  H04L1/1809

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

公开(公告)号：US20240394195A1

公开(公告)日：2024-11-28

申请号：US18665319

申请日：2024-05-15

Applicant: Rambus Inc.

Inventor： Steven C. WOO ,  Michael Raymond MILLER ,  Taeksang SONG ,  Wendy ELSASSER ,  Maryam BABAIE

IPC: G06F12/0895 ,  G06F12/084 ,  G06F13/16

Abstract: A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. The DRAM is configured to respond to at least two types of commands. A first type of command (cache data access command) seeks to access a cache line of data, if present in the DRAM cache. A second type of command (cache probe command) seeks to determine whether a cache line of data is present, but is not requesting the data be returned in response. In response to these types of access commands, the DRAM device is configured to receive cache tag query values and to compare stored cache tag values with the cache tag query values. A hit/miss (HM) interface/bus may indicate the result of the cache tag compare and stored cache line status bits to a controller.

公开(公告)号：US12147351B2

公开(公告)日：2024-11-19

申请号：US18139220

申请日：2023-04-25

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Mark D. Kellam

IPC: G06F12/10 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/1009 ,  G06F12/123 ,  G06F13/16

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

公开(公告)号：US12147345B2

公开(公告)日：2024-11-19

申请号：US18074217

申请日：2022-12-02

Applicant: Rambus Inc.

Inventor： Collins Williams ,  Michael Miller ,  Kenneth Wright

IPC: G06F12/08 ,  G06F12/0815 ,  G11C14/00

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.