公开(公告)号：US20140266322A1

公开(公告)日：2014-09-18

申请号：US14199313

申请日：2014-03-06

Applicant: STMICROELECTRONICS R&D (SHANGHAI) CO. LTD.

Inventor： Fei Wang ,  Wen Li Bai

IPC: H03K3/012

CPC classification number: H03K17/00 ,  H03K17/163

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract translation: 具有漏极和源极的驱动晶体管的栅极由包括感测电路的电路放电，该感测电路被配置为感测驱动晶体管的漏极 - 源极电压。 第一电流吸收通路耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较低的漏极 - 源极电压时，第一电流阱路径向驱动晶体管的栅极施加高放电电流。 第二电流吸收通路也耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较高的漏极 - 源极电压时，第二电流吸收通道被配置为向驱动晶体管的栅极施加低放电电流。

公开(公告)号：US08779736B2

公开(公告)日：2014-07-15

申请号：US12823101

申请日：2010-06-24

Applicant: Sarah Gao ,  David Peng

Inventor： Sarah Gao ,  David Peng

IPC: G05F1/575 ,  G06G7/26 ,  H01F27/42

CPC classification number: G05F1/575

Abstract: A linear voltage regulator includes a Miller frequency compensation having a movable zero, which tracks the frequency of the load pole as the load condition changes. The compensated voltage regulator maintains stability under variable load conditions. Because of the Miller effect, DC open-loop gain and bandwidth are not sacrificed for stability. The compensated voltage regulator can therefore maintain high power supply rejection ratio (PSRR).

Abstract translation: 线性电压调节器包括具有可移动零点的米勒频率补偿，其随着负载条件改变而跟踪负载极的频率。 补偿电压调节器在可变负载条件下保持稳定。 由于米勒效应，DC稳定性不会牺牲直流开环增益和带宽。 因此，补偿电压调节器可以保持高电源抑制比（PSRR）。

公开(公告)号：US20140165079A1

公开(公告)日：2014-06-12

申请号：US14180894

申请日：2014-02-14

Applicant: STMicroelectronics R&D (Shanghai) Co., Ltd.

Inventor： Christophe Quarre ,  Maoping Weng ,  Zhe Wu

IPC: G06F9/54

CPC classification number: G06F9/54 ,  G06F9/44521

Abstract: The present invention provides a technical solution for a unified driver used in a handheld device. An embodiment of the technical solution may comprise a unified driving method used in a handheld device, which method may comprise: determining driver types of currently installed hardware; setting a current dispatch table on the basis of the driver type and a unified dispatch table suitable for multiple hardware and driving corresponding hardware or software by calling the current dispatch table.

Abstract translation: 本发明提供了用于手持设备中的统一驱动程序的技术方案。 技术方案的实施例可以包括在手持设备中使用的统一驱动方法，该方法可以包括：确定当前安装的硬件的驱动器类型; 基于驱动程序类型设置当前调度表，并通过调用当前调度表来适用于多个硬件并驱动相应的硬件或软件的统一调度表。

公开(公告)号：US20140070788A1

公开(公告)日：2014-03-13

申请号：US14020949

申请日：2013-09-09

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Ansgar Pottbaecker ,  Panny Cai

IPC: G05F3/08

CPC classification number: G05F3/08 ,  G05F3/22 ,  G05F3/30

Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.

Abstract translation: 带隙参考电压发生器包括具有第一电阻器，第一分支和与第一分支平行的第二分支的双极组件。 第一分支包括具有耦合到固定电压的基极的第一双极晶体管。 第二分支包括具有耦合到固定电压的基极的第二双极晶体管和与第二双极晶体管串联耦合的第二电阻器。 差分模块耦合到第一和第二双极晶体管并且被配置为平衡第一和第二分支中的电流。 带隙参考电压在与第一电阻器连接的节点处输出。

公开(公告)号：US08624536B2

公开(公告)日：2014-01-07

申请号：US12892500

申请日：2010-09-28

Applicant: Zhongrui “Kevin” Zhao

Inventor： Zhongrui “Kevin” Zhao

IPC: H02H7/085 ,  H02K11/00

CPC classification number: H02K11/001 ,  B60L3/0061 ,  B60L2200/12 ,  H02H7/0838 ,  H02K11/20

Abstract: In one embodiment, a system for controlling a motor is disclosed. The system has a driver circuit configured to drive a motor, a current sensing impedance coupled to the driver circuit, and an overload detection circuit coupled to the current sending impedance that has a transistor and a detection output node.

Abstract translation: 在一个实施例中，公开了一种用于控制电动机的系统。 该系统具有被配置为驱动电动机的驱动器电路，耦合到驱动器电路的电流感测阻抗以及耦合到具有晶体管和检测输出节点的电流发送阻抗的过载检测电路。

公开(公告)号：US08319530B2

公开(公告)日：2012-11-27

申请号：US12408650

申请日：2009-03-20

Applicant: Jianhua Zhao ,  Sarah Gao

Inventor： Jianhua Zhao ,  Sarah Gao

IPC: H03B1/00

CPC classification number: H03F3/301 ,  H03F1/308 ,  H03F2200/18 ,  H03F2203/30081 ,  H03F2203/30114 ,  H03K19/0013

Abstract: A buffer circuit includes a biasing circuit operable to generate first and second biasing signals. A capacitive network includes an input adapted to receive an input signal and the capacitive network is operable responsive to the input signal to generate first and second bootstrapped signals. A push-pull stage includes first and second control inputs and an output. The push-pull stage is coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and is coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively. The push-pull stage is operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals.

Abstract translation: 缓冲电路包括可操作以产生第一和第二偏置信号的偏置电路。 电容网络包括适于接收输入信号的输入端，并且所述电容网络响应于所述输入信号而可操作以产生第一和第二自举信号。 推挽级包括第一和第二控制输入和输出。 推挽级耦合到偏置电路以分别在第一和第二控制输入上接收第一和第二偏置信号，并且耦合到电容网络以在第一和第二控制上接收第一和第二自举信号 输入。 推挽级可操作以响应于第一和第二自举信号在输出上产生缓冲的输出信号。

公开(公告)号：US08274417B2

公开(公告)日：2012-09-25

申请号：US12965651

申请日：2010-12-10

Applicant: Jianhua Zhao ,  Shawn Wang

Inventor： Jianhua Zhao ,  Shawn Wang

IPC: H03M1/66

CPC classification number: H03M1/682 ,  H03M1/765

Abstract: For coarse resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row are fed into multiplexers, wherein the multiplexers produce output voltages. DAC circuit designs extend the resolution of the output voltages by feeding them into a voltage interpolation amplifier. A method and apparatus are disclosed for implementing Gray code to design coarse DAC architecture for voltage interpolation such that the number of switches required by the circuit is significantly reduced, thereby decreasing required surface area, and improving glitch performance without increasing design complexity.

Abstract translation: 对于粗电阻串DAC，电阻串被放置在列和行的阵列中，每个电阻抽头连接到开关网络，并且解码器用于选择要闭合的开关，使得副DAC电压来自电阻器 抽头连接到选定的开关。 来自每行的电压被馈送到多路复用器中，其中多路复用器产生输出电压。 DAC电路设计通过将输出电压馈入电压内插放大器来扩展输出电压的分辨率。 公开了一种用于实现格雷码来设计用于电压内插的粗DAC架构的方法和装置，使得电路所需的开关数量显着减少，从而减少所需的表面积，并且在不增加设计复杂性的情况下改善毛刺性能。

公开(公告)号：US20090237125A1

公开(公告)日：2009-09-24

申请号：US12408650

申请日：2009-03-20

Applicant: Jianhua Zhao ,  Sarah Gao

Inventor： Jianhua Zhao ,  Sarah Gao

IPC: H03B1/00

CPC classification number: H03F3/301 ,  H03F1/308 ,  H03F2200/18 ,  H03F2203/30081 ,  H03F2203/30114 ,  H03K19/0013

Abstract: A buffer circuit includes a biasing circuit operable to generate first and second biasing signals. A capacitive network includes an input adapted to receive an input signal and the capacitive network is operable responsive to the input signal to generate first and second bootstrapped signals. A push-pull stage includes first and second control inputs and an output. The push-pull stage is coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and is coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively. The push-pull stage is operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals.

Abstract translation: 缓冲电路包括可操作以产生第一和第二偏置信号的偏置电路。 电容网络包括适于接收输入信号的输入端，并且所述电容网络响应于所述输入信号而可操作以产生第一和第二自举信号。 推挽级包括第一和第二控制输入和输出。 推挽级耦合到偏置电路以分别在第一和第二控制输入上接收第一和第二偏置信号，并且耦合到电容网络以在第一和第二控制上接收第一和第二自举信号 输入。 推挽级可操作以响应于第一和第二自举信号在输出上产生缓冲的输出信号。

公开(公告)号：US20070257924A1

公开(公告)日：2007-11-08

申请号：US11788395

申请日：2007-04-19

Applicant: Christophe Quarre ,  Li Haizhen ,  Chester Kwok-kee

Inventor： Christophe Quarre ,  Li Haizhen ,  Chester Kwok-kee

IPC: G06T15/00

CPC classification number: G06T15/00

Abstract: Due to the lack of 3D applications based on the OpenGL|ES standard, a desire exists to run 3D applications based on the OpenGL standard on OpenGL|ES mobile devices such as cellular telephones. To address this desire, one must be able to translate function calls between OpenGL and OpenGL|ES. In supporting this translation, and so as to ensure proper data state for the continued execution of the OpenGL application, global GL states which might be changed by an OpenGL|ES function used during translation are stored. The OpenGL to OpenGL|ES translation is then effectuated by substituting appropriate OpenGL|ES commands for OpenGL commands, and passing OpenGL|ES APIs for OpenGL|ES implementation. Thereafter, the global GL states which were previously saved are restored such that the performed translation does not adversely impact continued execution of the OpenGL configured application. This translation process supports OpenGL to OpenGL|ES translation with respect to a number of OpenGL APIs as well as some known extensions, such as: glBegin/glEnd paradigm, ArrayElement, Automatic Texture Coordinate Generation, Display List, and Multtexture.

Abstract translation: 由于缺乏基于OpenGL | ES标准的3D应用程序，基于OpenGL | ES移动设备（如手机）上的OpenGL标准运行3D应用程序的愿望。 为了解决这个愿望，必须能够在OpenGL和OpenGL | ES之间转换函数调用。 为了保证OpenGL应用程序的持续执行，为了确保正确的数据状态，可以存储可能由翻译期间使用的OpenGL | ES函数改变的全局GL状态。 然后通过为OpenGL命令替换适当的OpenGL | ES命令，并为OpenGL | ES实现传递OpenGL | ES API来实现OpenGL到OpenGL | ES翻译。 此后，恢复先前保存的全局GL状态，使得执行的转换不会对继续执行OpenGL配置的应用程序产生不利影响。 该翻译过程支持OpenGL与OpenGL API的OpenGL API翻译，以及一些已知的扩展，例如：glBegin / glEnd范例，ArrayElement，自动纹理坐标生成，显示列表和Multtexture。

公开(公告)号：US09568933B2

公开(公告)日：2017-02-14

申请号：US14020949

申请日：2013-09-09

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Ansgar Pottbaecker ,  Panny Cai

IPC: G05F3/16 ,  G05F3/08 ,  G05F3/30 ,  G05F3/22

CPC classification number: G05F3/08 ,  G05F3/22 ,  G05F3/30

Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.

Abstract translation: 带隙参考电压发生器包括具有第一电阻器，第一分支和与第一分支平行的第二分支的双极组件。 第一分支包括具有耦合到固定电压的基极的第一双极晶体管。 第二分支包括具有耦合到固定电压的基极的第二双极晶体管和与第二双极晶体管串联耦合的第二电阻器。 差分模块耦合到第一和第二双极晶体管并且被配置为平衡第一和第二分支中的电流。 带隙参考电压在与第一电阻器连接的节点处输出。