公开(公告)号：US09823290B2

公开(公告)日：2017-11-21

申请号：US14197247

申请日：2014-03-05

Applicant: Infineon Technologies AG

Inventor： Franz Fink ,  Alexander Koelpin ,  Harald Kuhn ,  Florian Oesterle

IPC: G01R31/04 ,  G01R31/01

CPC classification number: G01R31/04 ,  G01R31/016

Abstract: In accordance with one embodiment, a method for testing a plurality of electronic components is provided, including subdividing the plurality of electronic components into a plurality of first groups and subdividing the plurality of electronic components into a plurality of second groups. The method may further include measuring, for each first group, an electrical parameter of an interconnection of the components of the first group; measuring, for each second group, an electrical parameter of an interconnection of the components of the second group, and determining which electronic components of the plurality of electronic components have a predefined property, on the basis of the result of the measurement of the electrical parameter for the first groups and on the basis of the result of the measurement of the electrical parameter for the second groups.

公开(公告)号：US09735071B2

公开(公告)日：2017-08-15

申请号：US14835449

申请日：2015-08-25

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian Michael Erwin ,  Gary W. Maier

IPC: H01L21/66 ,  H01L21/48 ,  G01R31/04 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/04 ,  G01R31/046 ,  G01R31/2818 ,  G01R31/2884 ,  H01L21/486 ,  H01L22/14 ,  H01L22/34 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13

Abstract: A method of forming a temporary test structure for device fabrication is provided. The method is particularly useful for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects and for electrical testing. The suitable material for the temporary test structure is TiW for a single layer structure, or Cu or Cu alloy over Ti or TiW for a bilayer structure with thickness in a range of about 20 nm to 1200 nm. Excimer laser ablation can be used to form the temporary test structure. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance, and the substrate can be further processed with normal processes. The temporary test structure may contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

公开(公告)号：US09678134B2

公开(公告)日：2017-06-13

申请号：US14528115

申请日：2014-10-30

Applicant: NIDEC-READ CORPORATION

Inventor： Munehiro Yamashita

IPC: G01R31/04 ,  G01R3/00 ,  G01R31/28

CPC classification number: G01R31/04 ,  G01R3/00 ,  G01R31/2808

Abstract: A method for maintaining a contact of a connection jig for connecting between a target object to be subjected to an electrical test and a testing apparatus configured to conduct the electrical test on the target object includes: detecting a change in voltage upon supply of power for the electrical test to a test point on the target object through the contact; and issuing maintenance information indicating the contact is abnormal, upon detection of a portion where the voltage does not successively rise.

公开(公告)号：US09658281B2

公开(公告)日：2017-05-23

申请号：US14063414

申请日：2013-10-25

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Chen ,  Mincent Lee

IPC: G01R31/28 ,  G01R31/04 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/02 ,  G01B7/12

CPC classification number: G01R31/2834 ,  G01B7/12 ,  G01B2210/56 ,  G01R31/026 ,  G01R31/04 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2891 ,  G01R31/318513

Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.

公开(公告)号：US09658269B2

公开(公告)日：2017-05-23

申请号：US14685226

申请日：2015-04-13

Applicant: ADC Telecommunications, Inc.

Inventor： Joseph Polland ,  Joseph C. Coffey

IPC: H01R13/703 ,  G01R31/04 ,  G02B6/38 ,  H01R13/66 ,  H01R31/06 ,  H01R13/717 ,  H01R24/64

CPC classification number: G01R31/04 ,  G01R31/045 ,  G02B6/3895 ,  H01R13/665 ,  H01R13/703 ,  H01R13/7175 ,  H01R24/64 ,  H01R31/065

Abstract: Systems and methods for connectors with insertion counters are provided. In one embodiment, a connector comprises: an interface configured to interface with a corresponding interface of a port to communicate signals between the port and a cable attached to the connector; at least one switch configured to change from a first state to a second state when the connector is inserted into the port; and a microcontroller configured to record insertion events, wherein the microcontroller increments an insertion count stored within the microcontroller when the at least one switch transitions from the first state to the second state.

公开(公告)号：US09601424B2

公开(公告)日：2017-03-21

申请号：US14684664

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Rahul Agarwal ,  Jens Oswald ,  Sheng Feng Lu ,  Soon Leng Tan ,  Jeffrey Lam

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  G01R31/04

CPC classification number: H01L23/49827 ,  G01R31/04 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372

Abstract: A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.

公开(公告)号：US09588167B2

公开(公告)日：2017-03-07

申请号：US14570279

申请日：2014-12-15

Applicant: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO

Inventor： Masanori Kosugi

IPC: G01R31/04 ,  H04B1/18

CPC classification number: G01R31/04 ,  H04B1/18

Abstract: A receiver includes an internal antenna installed on a substrate and capable of receiving a wireless signal, and an external antenna connected to a connector, which is arranged on the substrate, and capable of receiving the wireless signal. A demodulator is arranged on the substrate and demodulates the wireless signals received through the internal antenna and the external antenna. An applying circuit is arranged on the substrate and applies a voltage to the external antenna via the connector. A disconnection detector is arranged on the substrate and detects whether the external antenna is disconnected based on a voltage or current applied by the applying circuit. The internal antenna forms a part of the applying circuit.

Abstract translation: 接收机包括安装在基板上并且能够接收无线信号的内部天线，以及连接到连接器的外部天线，其布置在基板上，并且能够接收无线信号。 解调器布置在基板上，并解调通过内部天线和外部天线接收的无线信号。 施加电路设置在基板上，并通过连接器向外部天线施加电压。 在基板上设置断线检测器，根据施加电路施加的电压或电流，检测外部天线是否断开。 内部天线形成施加电路的一部分。

公开(公告)号：US20170038420A1

公开(公告)日：2017-02-09

申请号：US15232756

申请日：2016-08-09

Applicant: The United States of America as represented by the Secretary of the Navy

Inventor： Eric Hodges ,  Ernest Coates ,  Angel Rosales-Ayala ,  Masato Taniguchi ,  Justin Cheung

IPC: G01R31/04 ,  G01R31/14 ,  G01R31/02

CPC classification number: G01R31/28 ,  G01R31/021 ,  G01R31/04 ,  G01R31/041 ,  G01R31/14

Abstract: Electronic test set embodiments and related methods are provided that can include a variety of safety components and/or processes which permit expandable or scalable automated testing of different types of equipment with or without installed sensitive, dangerous, vulnerable or expendable equipment. Embodiments can programmably or interface share measuring systems using expandable programmable interface systems that can scalably test a large number of components or electrical channels or bus lines. Embodiments can include multiple circuit board slot connectors adapted to receive programmable relay circuit cards that can selectively couple individual pins on ETS interface structures (e.g., cable connectors) to selected test equipment. Programmable relay circuit cards can be added to the ETS based on how many channels or bus connections are needed to interface with a system under test.

Abstract translation: 提供了电子测试集实施例和相关方法，其可以包括各种安全组件和/或过程，其允许具有或不具有安装的敏感，危险，易损或消耗性设备的不同类型设备的可扩展或可扩展的自动化测试。 实施例可以可编程地或使用可扩展的可编程接口系统来接口共享测量系统，该可扩展的可编程接口系统可以可扩展地测试大量组件或电气通道或总线。 实施例可以包括适于接收可选择性地将ETS接口结构（例如，电缆连接器）上的各个引脚耦合到所选择的测试设备的可编程继电器电路卡的多个电路板插槽连接器。 可编程继电器电路卡可以根据需要多少通道或总线连接与被测系统进行连接而添加到ETS。

公开(公告)号：US09551739B2

公开(公告)日：2017-01-24

申请号：US14582385

申请日：2014-12-24

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yoshihiro Osaki

IPC: G01R31/04 ,  H01R24/46 ,  H01R24/50 ,  H01R103/00

CPC classification number: G01R31/04 ,  H01R24/46 ,  H01R24/50 ,  H01R2103/00

Abstract: A coaxial connector including a connector main body is formed of an upper housing and a lower housing. An outer conductor includes a circular cylinder portion surrounding the periphery of a hole of the connector main body and configured to be inserted into an outer conductor of a mating coaxial connector. A main body portion is provided on the connector main body, and a fixation portion that is extended from the main body portion so as to sandwich the connector main body along with the main body portion. A fixed terminal is anchored to the connector main body. A movable terminal includes a fixation portion anchored to the connector main body, and a plate spring that extends from the fixation portion toward the fixed terminal and overlaps with the fixation portion at tip ends of the plate spring.

Abstract translation: 包括连接器主体的同轴连接器由上壳体和下壳体形成。 外导体包括围绕连接器主体的孔的周边的圆柱形部分，并被构造成插入配合同轴连接器的外导体中。 主体部分设置在连接器主体上，以及固定部分，其从主体部分延伸以便与主体部分一起夹持连接器主体。 固定终端固定在连接器主体上。 可移动端子包括固定到连接器主体的固定部分，以及从固定部分朝向固定端子延伸并且在板簧的尖端处与固定部分重叠的板簧。

公开(公告)号：US20160360634A1

公开(公告)日：2016-12-08

申请号：US15119033

申请日：2014-02-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Scott Edwards Holloway ,  Charles W. Cochran

IPC: H05K7/04 ,  G01R31/04 ,  H05K1/18

CPC classification number: H05K7/04 ,  G01R31/04 ,  H05K1/18 ,  H05K7/1432

Abstract: Circuit boards for an electronic device are described. In one implementation, the circuit board includes at least two holes at two locations on the circuit board. Each of the at least two holes has a conductive contact coupled to a voltage source through a resistor. The circuit board includes a microcontroller programmed to measure voltages at conductive contacts of the at least two holes, and determine a position of the circuit board, when positioned on a conductive chassis of the electronic device, based on the measured voltages. The position of the circuit board may be one of a first end and a second end, and in between the first end and the second end, of the conductive chassis.

Abstract translation: 对电子设备的电路板进行说明。 在一个实施方式中，电路板在电路板上的两个位置包括至少两个孔。 所述至少两个孔中的每一个具有通过电阻器耦合到电压源的导电接触。 电路板包括被编程为测量至少两个孔的导电触点处的电压的微控制器，并且当基于所测量的电压来确定位于电子设备的导电底盘上时确定电路板的位置。 电路板的位置可以是导电底盘的第一端和第二端之一，并且在第一端和第二端之间。