公开(公告)号：US11875167B2

公开(公告)日：2024-01-16

申请号：US17209100

申请日：2021-03-22

申请人： Nubix, Inc.

发明人： Michael Gray ,  Tom Yates ,  Rachel Taylor

IPC分类号： G06F9/455 ,  G06F8/654 ,  G06F12/14 ,  G06F8/61

CPC分类号： G06F9/45508 ,  G06F8/654 ,  G06F9/45516 ,  G06F9/45533 ,  G06F12/1425 ,  G06F8/61 ,  G06F12/1441

摘要： A method includes: accessing a set of hardware parameters characterizing an embedded device; identifying a set of supported container functions based on the set of hardware parameters; accessing a selection of container functions; identifying a set of selected container functions based on the selection of container functions and the set of supported container functions; generating a hardware abstraction layer (HAL) including a set of libraries supporting the set of selected container functions; generating a container runtime environment (CRE) configured to execute, at the embedded device, a containerized application via the HAL, the containerized application including the set of selected container functions; installing the HAL and the CRE onto the embedded device; installing the containerized application onto the embedded device via the CRE; and at the embedded device, executing the containerized application via the CRE and the HAL.

公开(公告)号：US11860795B2

公开(公告)日：2024-01-02

申请号：US16792901

申请日：2020-02-18

申请人： Arm Limited

发明人： Itay Zacay ,  Adi Kachal ,  Roee Friedman ,  Dvir Shalom Marcovici ,  Uri Eliyahu

IPC分类号： G06F12/14 ,  G06F12/02

CPC分类号： G06F12/1416 ,  G06F12/0238 ,  G06F12/1441 ,  G06F2212/1052

摘要： Device, system, and method of determining memory requirements and tracking memory usage. A method includes: dynamically modifying, in an iterative process including two or more iterations, a maximum size of Random Access Memory (RAM) that a Memory Protection Unit (MPU) authorizes an executable program code to access. In each iteration, the method includes running that executable program code while the MPU enforces a different maximum size of RAM, and monitoring whether the executable program code attempted to access a RAM memory address that is beyond that maximum size of RAM in that iteration. Based on such iterations, the method determines a minimum size of RAM that is required for that executable program code to run without causing a memory access fault.

公开(公告)号：US20230409205A1

公开(公告)日：2023-12-21

申请号：US18339812

申请日：2023-06-22

申请人： Rambus Inc.

发明人： Aws Shallal ,  Micheal Miller ,  Stephen Horn

IPC分类号： G06F3/06 ,  G11C14/00 ,  G06F12/14 ,  G06F11/00 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16

CPC分类号： G06F3/0613 ,  G06F3/0611 ,  G11C14/0009 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1441 ,  G06F11/00 ,  G11C5/04 ,  G11C11/005 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0802 ,  G06F13/1673 ,  G06F13/1668 ,  G11C7/1051

摘要： Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US20230315648A1

公开(公告)日：2023-10-05

申请号：US17709867

申请日：2022-03-31

申请人： Intel Corporation

发明人： David M. Durham

IPC分类号： G06F12/14 ,  G06F12/0882 ,  G06F9/455

CPC分类号： G06F12/1441 ,  G06F12/145 ,  G06F12/1458 ,  G06F12/0882 ,  G06F9/45558 ,  G06F2212/7201 ,  G06F2009/45583 ,  G06F2009/45587

摘要： Systems, methods, and apparatuses for implementing micro-context based trust domains are described. In one example, a system includes a hardware processor core to implement a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of protected memory, and assign a micro-context identification value, that is not readable by privileged system code that is to execute on the hardware processor core, to each granule of a plurality of granules of physical memory of the protected memory (e.g., where a granule is a proper subset of a page of memory relating to a single object in memory); and a memory management circuit coupled between the hardware processor core and the physical memory, wherein the memory management circuit is to prevent data in the protected memory having a first micro-context identification value from being accessed by code based on the code having a different micro-context identification value.

公开(公告)号：US20230281135A1

公开(公告)日：2023-09-07

申请号：US18314999

申请日：2023-05-10

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Zhangkai ZHANG ,  Dongdong YAO ,  Cong WANG ,  Yihua TAN

IPC分类号： G06F12/14 ,  G06F12/1036 ,  G06F12/1009

CPC分类号： G06F12/1441 ,  G06F12/1036 ,  G06F12/1009

摘要： A method for configuring an address translation relationship is disclosed. The method is applied to a computer system. A rich execution environment REE and a trusted execution environment TEE are deployed in the computer system, a virtual machine VM and a virtual machine manager VMM are deployed in the REE, and a secure partition SP and a secure partition manager SPM are deployed in the TEE. The method includes: The VMM transfers a first address translation relationship to the SPM. The first address translation relationship includes an address translation relationship from an intermediate physical address IPA allocated to the VM to a physical address PA, so that the SPM performs IPA-to-PA address translation based on the first address translation relationship when transmitting data from the SP to the VM. The PA is a memory address. The method simplifies a process in which the SPM establishes an IPA-to-VA address mapping relationship.

公开(公告)号：US11748274B2

公开(公告)日：2023-09-05

申请号：US17014239

申请日：2020-09-08

申请人： Nuvoton Technology Corporation

发明人： Yu-Shan Li

IPC分类号： G06F12/14 ,  G06F13/16 ,  G06F21/79 ,  G06F21/75 ,  G06F12/02 ,  H03M13/19 ,  H03M13/11

CPC分类号： G06F12/1441 ,  G06F12/0246 ,  G06F13/1647 ,  G06F13/1668 ,  G06F21/755 ,  G06F21/79 ,  H03M13/1108 ,  H03M13/19 ,  G06F2212/40

摘要： A memory device includes a memory array and a memory controller. The memory array includes a first memory bank, a second memory bank, and a third memory bank. The first memory bank includes a first sub memory bank. The second memory bank includes a second sub memory bank. The memory controller, according to a write command from a host, writes first data from the host to the first memory bank and second data to the second memory bank at the same time, and writes a first Hamming weight of the first data to the third memory bank. The second data is the inverse of the first data.

公开(公告)号：US11741253B2

公开(公告)日：2023-08-29

申请号：US16262998

申请日：2019-01-31

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Sridhar Bandi ,  Suhas Shivanna

IPC分类号： G06F21/62 ,  G06F21/60 ,  G06F12/14 ,  G06F8/41

CPC分类号： G06F21/6245 ,  G06F12/1408 ,  G06F12/1441 ,  G06F21/602 ,  G06F8/41

摘要： A technique includes, in response to an exception occurring in the execution of a process on a computer, invoking an operating system service. The operating system service is used to sanitize data that is associated with the process and is stored in a memory of the computer. The data is associated with sensitive information.

公开(公告)号：US11720486B2

公开(公告)日：2023-08-08

申请号：US16990926

申请日：2020-08-11

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Yen-Ju Lu ,  Chao-Wei Huang

IPC分类号： G06F12/02 ,  G06F12/14 ,  G06F9/30 ,  G06F13/40 ,  G06F12/0846

CPC分类号： G06F12/0246 ,  G06F9/30105 ,  G06F12/0848 ,  G06F12/1441 ,  G06F13/4068

摘要： The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.

公开(公告)号：US11711201B2

公开(公告)日：2023-07-25

申请号：US17213568

申请日：2021-03-26

申请人： Intel Corporation

发明人： Andrew James Weiler ,  David M. Durham ,  Michael D. LeMay ,  Sergej Deutsch ,  Michael E. Kounavis ,  Salmin Sultana ,  Karanvir S. Grewal

IPC分类号： H04L9/06 ,  G06F9/50 ,  G06F12/14 ,  H04L9/08 ,  H04L9/32 ,  G06F12/121

CPC分类号： H04L9/0618 ,  G06F9/5016 ,  G06F12/121 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1458 ,  G06F2212/7207

摘要： In one embodiment, an encoded pointer is constructed from a stack pointer that includes offset. The encoded pointer includes the offset value and ciphertext that is based on encrypting a portion of a decorated pointer that includes a maximum offset value. Stack data is encrypted based on the encoded pointer, and the encoded pointer is stored in a stack pointer register of a processor. To access memory, a decoded pointer is constructed based on decrypting the ciphertext of the encoded pointer and the offset value. Encrypted stack data is accessed based on the decoded pointer, and the encrypted stack is decrypted based on the encoded pointer.

公开(公告)号：US11698996B2

公开(公告)日：2023-07-11

申请号：US17500819

申请日：2021-10-13

申请人： Google LLC

发明人： Osman Koyuncu ,  William Alexander Drewry

IPC分类号： G06F21/60 ,  G06F21/72 ,  G06F21/44 ,  G06F21/85 ,  G06F12/14 ,  G06F21/73 ,  H04L9/14 ,  G06F21/71

CPC分类号： G06F21/85 ,  G06F12/1408 ,  G06F12/1441 ,  G06F21/602 ,  G06F21/72 ,  G06F21/73 ,  H04L9/14 ,  G06F2212/1052 ,  G06F2212/402

摘要： Methods and systems are described that secure application data being maintained in transient data buffers that are located in a memory that is freely accessible to other components, regardless as to whether those components have permission to access the application data. The system includes an application processor, a memory having a portion configured as a transient data buffer, a hardware unit, and a secure processor. The hardware unit accesses the transient data buffer during execution of an application at the application processor. The secure processor is configured to manage encryption of the transient data buffer as part of giving the hardware unit access to the transient data buffer.