利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

80 条记录 (耗时 0.025 秒)

    Binary adder and multiplier circuit
    13.
    发明授权
    Binary adder and multiplier circuit 有权
    二进制加法器和乘法器电路

    公开(公告)号：US08933731B2

    公开(公告)日：2015-01-13

    申请号：US14077198

    申请日：2013-11-11

    申请人： Rohit Goyal ,  Amit Kumar Dey ,  Naman Gupta

    发明人： Rohit Goyal ,  Amit Kumar Dey ,  Naman Gupta

    IPC分类号： H03B19/00 ,  G06F7/527 ,  G06F7/507

    CPC分类号： G06F7/5272 ,  G06F7/507

    摘要： An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.

    摘要翻译： 加法器电路包括第一至第四二位加法器模块，以及第一至第三结果多路复用块，用于接收和添加第一和第二二进制值以产生最终和。 乘法器和乘法器的乘法器电路包括复用器，连接到多路复用器的编码器，连接到编码器的移位器和连接到编码器的累加器，用于接收乘法器并被乘法并产生乘积。

    Method and apparatus having a measured value input for applying a measured value
    14.
    发明授权
    Method and apparatus having a measured value input for applying a measured value 有权
    具有用于施加测量值的测量值输入的方法和装置

    公开(公告)号：US08443019B2

    公开(公告)日：2013-05-14

    申请号：US12561795

    申请日：2009-09-17

    申请人： Manfred Kopp

    发明人： Manfred Kopp

    IPC分类号： G06F7/00 ,  G06F15/00

    CPC分类号： G06F7/4876 ,  G06F7/49963 ,  G06F7/5272 ,  G06F2207/3852 ,  H03M7/24

    摘要： The invention pertains to a device such as a sensor, operator device, communication device, or a liquid level metering device, with a measured value input to apply a measured value. The device includes at least a first memory region to provide for an adjustment factor, and a computer, which is designed and/or controlled to multiply a first whole number by a floating-point number to obtain a product of the multiplication, while the first whole number corresponds either to the applied measured value or the provided adjustment factor; and, the floating-point number corresponds to the other measured value or to the adjustment factor. The computer has a second memory region for the storing of the floating-point number in a format of a second whole number, and the computer is designed and/or controlled to carry out a multiplication of the first whole number and the second whole number.

    摘要翻译： 本发明涉及诸如传感器，操作者装置，通信装置或液位计量装置的装置，具有测量值输入以应用测量值。 该设备至少包括一个提供调整因子的第一存储器区域和一个被设计和/或控制以将第一整数乘以浮点数来获得乘法乘积的计算机，而第一个 整数对应于应用的测量值或提供的调整因子; 并且，浮点数对应于另一个测量值或调整因子。 计算机具有用于以第二整数的格式存储浮点数的第二存储器区域，并且计算机被设计和/或控制以执行第一整数和第二整数的乘法。

    Specialized processing block for programmable logic device
    15.
    发明申请
    Specialized processing block for programmable logic device 有权
    可编程逻辑器件专用处理块

    公开(公告)号：US20070185952A1

    公开(公告)日：2007-08-09

    申请号：US11447472

    申请日：2006-06-05

    申请人： Martin Langhammer ,  Kwan Yee Martin Lee ,  Orang Azgomi ,  Keone Streicher ,  Yi-Wen Lin

    发明人： Martin Langhammer ,  Kwan Yee Martin Lee ,  Orang Azgomi ,  Keone Streicher ,  Yi-Wen Lin

    IPC分类号： G06F7/00

    CPC分类号： H03K19/17732 ,  G06F7/527 ,  G06F7/5272

    摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.

    摘要翻译： 用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。 这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。 专用处理块还具有输入和输出级以及环回功能，以允许块被配置用于各种数字信号处理操作。

    Modular arithmetic coprocessor comprising two multiplication circuits working in parallel
    16.
    发明申请
    Modular arithmetic coprocessor comprising two multiplication circuits working in parallel 审中-公开
    模块化算术协处理器包括并行工作的两个乘法电路

    公开(公告)号：US20020178196A1

    公开(公告)日：2002-11-28

    申请号：US09991494

    申请日：2001-11-21

    发明人： Guy Monier

    IPC分类号： G06F007/38

    CPC分类号： G06F7/5272 ,  G06F7/728 ,  G06F2207/382

    摘要： A coprocessor including a first multiplication circuit and a second multiplication circuit with a series input to receive n bits and a series output to give nnullk bits. The coprocesser also includes addition and multiplexing circuits enabling the data elements produced by the multiplication circuits to be added up with one another and with other data elements encoded on n bits. The invention makes parallel use of the multiplication circuits to carry out modular or non-modular operations on pieces of binary data having n bits or more.

    摘要翻译： 一种协处理器，包括第一乘法电路和具有串行输入以接收n位的第二乘法电路和串行输出以给出n + k位。 协处理器还包括加法和多路复用电路，使得乘法电路产生的数据元素可以彼此相加，并与n位编码的其他数据元素相加。 本发明并行使用乘法电路对具有n位或更多位的二进制数据进行模块化或非模块化操作。

    Apparatus and method for a multiplier unit with high component utilization
    17.
    发明授权
    Apparatus and method for a multiplier unit with high component utilization 失效
    具有高组件利用率的乘法器单元的装置和方法

    公开(公告)号：US5889691A

    公开(公告)日：1999-03-30

    申请号：US782001

    申请日：1997-01-06

    申请人： Alan Gatherer ,  Carl E. Lemonds

    发明人： Alan Gatherer ,  Carl E. Lemonds

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5272

    摘要： In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multiplier B applied to the gate component control terminal. Partial products are grouped by multiplicand digits and each digit is applied, through delay components determined by the order of the digit, to first terminals of an associated adder components. Output signals from each adder component is transmitted through a plurality of delay components and applied to second input terminals of the same adder component. In this manner, partial products A.sub.p *B.sub.q are assembled and the partial products (A.sub.0 + . . . A.sub.M)*B.sub.q =A*B.sub.q can be applied to the summation unit in a single period. When the multiplier is an integer multiple of the multiplicand, the implementation is particularly convenient.

    摘要翻译： 在具有预处理器级，乘法器级和求和级的乘法器单元中，乘法器级包括移位寄存器，用于以由施加到门的乘法器B的位信号确定的方式可控地发送被乘数A的门分量 组件控制终端。 部分产品按被乘数分组，每个数字通过由数字顺序确定的延迟分量应用于相关加法器分量的第一个终端。 来自每个加法器分量的输出信号通过多个延迟分量传输并被施加到相同加法器分量的第二输入端。 以这种方式，部分乘积Ap * Bq被组装，并且部分乘积（A0 +。。AM）* Bq = A * Bq可以在单个周期内应用于求和单元。 当乘数是被乘数的整数倍时，实现特别方便。

    Parallel shift and add circuit and method
    19.
    发明授权
    Parallel shift and add circuit and method 失效
    并行移位和加法电路及方法

    公开(公告)号：US5390135A

    公开(公告)日：1995-02-14

    申请号：US158646

    申请日：1993-11-29

    申请人： Ruby B. Lee ,  Joel D. Lamb

    发明人： Ruby B. Lee ,  Joel D. Lamb

    IPC分类号： G06F7/50 ,  G06F7/508 ,  G06F7/52 ,  G06F7/53 ,  G06F7/57 ,  G06F7/575 ,  G06F9/302 ,  G06F7/38

    CPC分类号： G06F7/5272 ,  G06F7/508 ,  G06F7/57 ,  G06F7/575 ,  G06F9/30014 ,  G06F9/30036 ,  G06F2207/3828 ,  G06F7/49921 ,  G06F7/49963

    摘要： An apparatus for combining the contents of an X register, shifted by m places, with the contents of a Y register to generate a result Z. The functional unit can also be configured to perform parallel operations on sub-operands in the X and Y registers. The division of the apparatus into sub-operands is controlled by a mask which specifies the boundary of the sub-operands. The shifting operation is accomplished by multiplexers that connect the p.sup.th bit of the X register to the adder stage that operates on bit Y.sub.p-m of the Y register. Circuitry is provided at the boundary of the sub-operands to prevent the bit signals corresponding to the X register from being routed across a sub-operand boundary. Similarly, circuitry is provided for preventing the carry output of an adder stage that operates on one sub-operand from being propagated to an adder stage that operates on another sub-operand.

    摘要翻译： 一种用于将移位了m个位置的X寄存器的内容与Y寄存器的内容组合以生成结果Z的装置。功能单元还可以被配置为对X和Y寄存器中的子操作数执行并行操作 。 将设备划分为子操作数由一个指定子操作数边界的掩码控制。 移位操作通过将X寄存器的第p位连接到对Y寄存器的位Yp-m进行操作的加法器级的复用器来实现。 在子操作数的边界处提供电路，以防止与X寄存器相对应的位信号跨越子操作数边界。 类似地，提供电路用于防止在一个子操作数上操作的加法器级的进位输出传播到对另一个子操作数进行操作的加法器级。

    One-dimensional interpolation circuit and method based on modification of a parallel multiplier
    20.
    发明授权
    One-dimensional interpolation circuit and method based on modification of a parallel multiplier 失效
    基于并行乘法器修改的一维插值电路及方法

    公开(公告)号：US5148381A

    公开(公告)日：1992-09-15

    申请号：US651738

    申请日：1991-02-07

    申请人： David L. Sprague

    发明人： David L. Sprague

    IPC分类号： G06F7/53 ,  G06F7/506 ,  G06F17/17

    CPC分类号： G06F17/17 ,  G06F7/5272 ,  G06F7/544

    摘要： An interpolator array having a plurality of interpolator array cells is provided for receiving first and second input values to be interpolated and an interpolator weight term, to provide an interpolated output. A bit of each of the two input values to be interpolated is received by an interpolator array cell and applied to a selecting circuit within a cell of the interpolator array. Additionally, an interpolation weight bit of the interpolation weight term is applied to the selection circuit. The selecting circuit applies either the input bit of the first input value or the input bit of the second input value to an adder within the interpolator cell in accordance with the value of the interpolation weight bit. An interpolator array cell also receives a partial product input and a carry-in input and applies these additional inputs to the adder. The adder provides a partial product output and a carry-out in accordance with the applied inputs.

    摘要翻译： 提供了具有多个内插器阵列单元的内插器阵列，用于接收待内插的第一和第二输入值和内插器加权项，以提供内插输出。 要插值的两个输入值中的每一个的一位被内插器阵列单元接收并且被施加到内插器阵列的单元内的选择电路。 此外，插值加权项的内插加权比特被施加到选择电路。 选择电路根据插补权重位的值将第一输入值的输入位或第二输入值的输入位应用到内插器单元内的加法器。 内插器阵列单元还接收部分积输入和进位输入，并将这些附加输入施加到加法器。 加法器根据应用的输入提供部分乘积输出和进位输出。