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公开(公告)号：US4092522A
公开(公告)日：1978-05-30
申请号：US756463
申请日：1977-01-03
申请人： Homer Warner Miller
发明人： Homer Warner Miller
IPC分类号： G01R31/3185 , G06F11/10 , G06F11/30 , H03K21/02 , H03K21/40
CPC分类号： G06F11/10 , G01R31/318527 , H03K21/026 , H03K21/40 , H03K23/58
摘要： A 5-bit D-type master/slave counter/shift register with buffered outputs is disclosed. The counter implements the load, count up, count down, and reset functions and also has the capability to be reconfigured into an inverting serial shift register for Non-Functional Test (NFT) techniques. In addition, the fifth bit may optionally be removed from the counter logic and used as a parity bit, although it will be necessary to use some external logic to implement this parity function.
摘要翻译： 公开了一种具有缓冲输出的5位D型主/从计数器/移位寄存器。 计数器实现负载，递增计数，倒计时和复位功能，并且还具有重新配置为用于非功能测试（NFT）技术的反相串行移位寄存器的能力。 此外，可以可选地从计数器逻辑中移除第五位并将其用作奇偶校验位，但是有必要使用一些外部逻辑来实现该奇偶校验功能。
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公开(公告)号：US3700916A
公开(公告)日：1972-10-24
申请号：US3700916D
申请日：1971-11-15
发明人： VITTOZ ERIC ANDRE
摘要： A logical frequency divider comprising at least one stage of division by two consisting of four logical gates A, B, C and D, the gates being connected as follows: the output from the first gate A controls an input to the second gate B; the output from the second gate B controls an input to the first gate A and an input to the third gate C; the output from the third gate C controls a second input to the first gate A, a second input to the second gate B and an input to the fourth gate D; the output from the fourth gate D controls a third input to the second gate B, a second input to the third gate C. The input signal to the stage of division by two controls a third input to the third gate C and a second input to the fourth gate D.
摘要翻译： 一种逻辑分频器，包括由四个逻辑门A，B，C和D组成的至少一个除法阶段，门被连接如下：来自第一门A的输出控制到第二门B的输入; 来自第二栅极B的输出控制到第一栅极A的输入和到第三栅极C的输入; 来自第三栅极C的输出控制到第一栅极A的第二输入，第二栅极B的第二输入和到第四栅极D的输入; 来自第四栅极D的输出控制到第二栅极B的第三输入，第二输入到第三栅极C.通过两个除法阶段的输入信号控制到第三栅极C的第三输入和第二输入 第四门D.
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公开(公告)号：US3238461A
公开(公告)日：1966-03-01
申请号：US31562963
申请日：1963-10-11
申请人： RCA CORP
发明人： MERRIAM ANN S
CPC分类号： H03K23/58
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14.发明申请公开(公告)号：US20190050019A1
公开(公告)日：2019-02-14
申请号：US15674242
申请日：2017-08-10
申请人： Ambiq Micro, Inc.
CPC分类号： G06F1/08 , G06F1/12 , G06F13/00 , G06F13/4291 , H03K23/58
摘要： A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.
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公开(公告)号：US09705507B1
公开(公告)日：2017-07-11
申请号：US15158622
申请日：2016-05-19
发明人： Dinesh Jain
CPC分类号： H03K21/026 , H03K5/05 , H03K23/58
摘要： Disclosed examples include frequency divider circuits to divide a high frequency first clock signal to generate an output clock signal at a lower frequency, including a delay circuit to provide a delayed clock signal, a divider circuit to provide a divided clock signal, a sub-sampling circuit to sub-sample the first clock signal with the divided clock signal, and a feedback circuit to set the delay value of the adjustable delay circuit according to the sub-sampled output signal.
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公开(公告)号：US09294099B2
公开(公告)日：2016-03-22
申请号：US14141458
申请日：2013-12-27
申请人： Rohit Goyal , Deepak Kumar Behera , Naman Gupta
发明人： Rohit Goyal , Deepak Kumar Behera , Naman Gupta
CPC分类号： H03K23/588 , H03K19/0008 , H03K21/10 , H03K21/12 , H03K23/58
摘要： A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.
摘要翻译： 混合计数器产生多位混合计数器值。 混合计数器包括两个或多个异步计数器，每个异步计数器被配置为生成多比特混合计数器值的比特的子集。 异步计数器由逻辑门和时钟门控电路互连。 逻辑门根据以前的异步计数器产生的位产生异步逻辑值。 时钟门控电路重新计时异步逻辑值以产生用于切换下一个异步计数器的同步逻辑值。 混合计数器的功能比传统的异步计数器更精确，功耗比传统的同步计数器少。
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公开(公告)号：US20140306740A1
公开(公告)日：2014-10-16
申请号：US13479471
申请日：2012-05-24
申请人： Matthew C. Guyton
发明人： Matthew C. Guyton
CPC分类号： H03K23/58 , H03K23/667
摘要： Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.
摘要翻译： 描述了基于从接收信号产生的时间交织信号的多模式分频器和事件计数器。 对于分频器，从接收的时钟信号产生的每个时间交织的时钟信号被提供给位计数器，并且来自每个位计数器的输出信号被提供给多路复用器。 多路复用器选择模块控制来自位计数器的输出信号中的哪一个在时间上在多路复用器的输出处呈现。 时间交织的时钟信号中的位的转换频率允许诸如位计数器之类的各种电路部件被实现为CMOS部件。 因此，分频器比在高时钟频率下工作的常规分频器电路更省电。
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公开(公告)号：US08847637B1
公开(公告)日：2014-09-30
申请号：US13479471
申请日：2012-05-24
申请人： Matthew C. Guyton
发明人： Matthew C. Guyton
CPC分类号： H03K23/58 , H03K23/667
摘要： Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.
摘要翻译： 描述了基于从接收信号产生的时间交织信号的多模式分频器和事件计数器。 对于分频器，从接收的时钟信号产生的每个时间交织的时钟信号被提供给位计数器，并且来自每个位计数器的输出信号被提供给多路复用器。 多路复用器选择模块控制来自位计数器的输出信号中的哪一个在时间上在多路复用器的输出处呈现。 时间交织的时钟信号中的位的转换频率允许诸如位计数器之类的各种电路部件被实现为CMOS部件。 因此，分频器比在高时钟频率下工作的常规分频器电路更省电。
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公开(公告)号：US07876873B2
公开(公告)日：2011-01-25
申请号：US12477083
申请日：2009-06-02
申请人： Hong-Yean Hsieh
发明人： Hong-Yean Hsieh
摘要： An asynchronous ping-pong counter is disclosed. The asynchronous ping-pong counter comprises a first asynchronous counter, a second synchronous counter, and a controller, the asynchronous ping-pong counter operates between a first state and a second state. In the first state, the first asynchronous counter counts a first number of clock edges of a fast clock signal, and the second asynchronous counter holds a first counter output value. In the second state, the second asynchronous counter counts a second number of clock edges of the fast clock signal, and the first asynchronous counter holds a second counter output value. The controller determines a state transition based on a sampling of a slow clock signal by the fast clock signal.
摘要翻译： 公开了一种异步乒乓计数器。 异步乒乓计数器包括第一异步计数器，第二同步计数器和控制器，异步乒乓计数器在第一状态和第二状态之间操作。 在第一状态下，第一异步计数器对快时钟信号的第一数量的时钟边缘进行计数，而第二异步计数器保持第一计数器输出值。 在第二状态下，第二异步计数器计数快速时钟信号的第二数量的时钟边沿，并且第一异步计数器保持第二计数器输出值。 控制器基于快速时钟信号的慢时钟信号的采样来确定状态转换。
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公开(公告)号：US20090307518A1
公开(公告)日：2009-12-10
申请号：US12436765
申请日：2009-05-06
申请人： Hong-Yean Hsieh
发明人： Hong-Yean Hsieh
IPC分类号： G06F1/06
CPC分类号： H03L7/091 , G04F10/005 , H03K5/1534 , H03K21/023 , H03K23/58 , H03L7/10 , H03L2207/50
摘要： A method for estimating a timing difference between a first clock signal and a second clock signal is disclosed. The estimating method comprising: generating an edge signal by detecting an edge of the second clock signal by sampling the second clock signal using the first clock signal; generating a delayed edge signal by a further sampling of the second clock signal using the first clock signal; generating a first intermediate code by counting a number of clock edges of the first clock signal within a duration defined by the edge signal using an asynchronous counter; generating a second intermediate code to represent a timing difference between the second clock signal and the delayed edge signal using a time-to-digital converter; and generating an output code using a weighted sum of the first intermediate code and the second intermediate code.
摘要翻译： 公开了一种用于估计第一时钟信号和第二时钟信号之间的定时差的方法。 所述估计方法包括：通过使用所述第一时钟信号对所述第二时钟信号进行采样来检测所述第二时钟信号的边沿来产生边沿信号; 通过使用第一时钟信号进一步采样第二时钟信号来产生延迟边沿信号; 通过使用异步计数器在由边缘信号限定的持续时间内对第一时钟信号的时钟边缘数进行计数来产生第一中间代码; 使用时间 - 数字转换器生成第二中间代码以表示第二时钟信号和延迟边沿信号之间的定时差; 以及使用所述第一中间代码和所述第二中间代码的加权和来生成输出代码。
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