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    SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE
    14.
    发明申请
    SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE 有权
    半导体芯片和半导体器件

    公开(公告)号：US20150303924A1

    公开(公告)日：2015-10-22

    申请号：US14754998

    申请日：2015-06-30

    申请人： RENESAS ELECTRONICS CORPORATION

    发明人： Tomoaki ISOZAKI

    IPC分类号： H03K19/0185 ,  H01L25/07 ,  H03K3/038

    CPC分类号： H03K19/018592 ,  H01L25/07 ,  H01L27/092 ,  H01L29/78 ,  H01L2924/0002 ,  H03K3/038 ,  H03K19/018521 ,  H01L2924/00

    摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area.

    摘要翻译： 半导体器件包括以第一电源电压工作的第一半导体芯片和以低于第一电源电压的第二电源电压工作的第二半导体芯片，以向第一半导体芯片提供第二电源电压。 根据本发明的半导体芯片方便地用于制造半导体器件。 第一半导体芯片包括一个包括第一晶体管和第二晶体管的输出电路，其互相串联并互补地开或关。 输出电路将信号输出到第一外部输出端子。 第一半导体芯片还包括与第一和第二晶体管串联连接的第三晶体管，并且具有连接到第二输出端子的栅电极。 与在不同工作电压下工作的多个半导体芯片相互连接并将其用于半导体器件的情况相比，整个芯片面积减小，该半导体器件具有以不同于各个工作电压的电压工作的输入/输出缓冲器 导致芯片面积增加。

    Semiconductor chip and semiconductor device
    15.
    发明授权
    Semiconductor chip and semiconductor device 有权
    半导体芯片和半导体器件

    公开(公告)号：US09099330B2

    公开(公告)日：2015-08-04

    申请号：US13735661

    申请日：2013-01-07

    申请人： Renesas Electronics Corporation

    发明人： Tomoaki Isozaki

    IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/094 ,  H01L25/07 ,  H01L27/092 ,  H01L29/78 ,  H03K3/038

    CPC分类号： H03K19/018592 ,  H01L25/07 ,  H01L27/092 ,  H01L29/78 ,  H01L2924/0002 ,  H03K3/038 ,  H03K19/018521 ,  H01L2924/00

    摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.

    摘要翻译： 半导体器件包括以第一电源电压工作的第一半导体芯片和以低于第一电源电压的第二电源电压工作的第二半导体芯片，以向第一半导体芯片提供第二电源电压。 第一半导体芯片包括一个包括第一晶体管和第二晶体管的输出电路，其互相串联并互补地开或关。 输出电路将信号输出到第一外部输出端子。 第一半导体芯片还包括与第一和第二晶体管串联连接的第三晶体管，并且具有连接到第二输出端子的栅电极。

    SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE
    16.
    发明申请
    SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20130154706A1

    公开(公告)日：2013-06-20

    申请号：US13735661

    申请日：2013-01-07

    申请人： Renesas Electronics Corporation

    发明人： Tomoaki ISOZAKI

    IPC分类号： H01L25/07 ,  H03K3/038

    CPC分类号： H03K19/018592 ,  H01L25/07 ,  H01L27/092 ,  H01L29/78 ,  H01L2924/0002 ,  H03K3/038 ,  H03K19/018521 ,  H01L2924/00

    摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area.

    Level-sensitive two-phase single-wire latch controllers without contention
    20.
    发明授权
    Level-sensitive two-phase single-wire latch controllers without contention 有权

    公开(公告)号：US09698784B1

    公开(公告)日：2017-07-04

    申请号：US15201048

    申请日：2016-07-01

    申请人： Altera Corporation

    发明人： Dana How

    IPC分类号： H03K19/00 ,  H03K19/02 ,  H03K19/0175 ,  H03K3/038

    CPC分类号： H03K19/0175 ,  G06F9/3869 ,  H03K3/038 ,  H03K19/0966

    摘要： Systems and methods are described for a contention-free single-wire latch controller that includes first and second bidirectional signal pins (e.g., the L and R pins in the FIGS), a latch enable output pin (or signal), E, and a decision element (such as a NAND or a NOR gate). A first driving transistor may be coupled between the first bidirectional signal pin and a power rail. A second driving transistor may be coupled between the second bidirectional signal pin and the power rail. A first half-latch may be coupled to the first bidirectional signal pin. A second half-latch may be coupled to the second bidirectional signal pin.