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公开(公告)号：US09369265B1
公开(公告)日：2016-06-14
申请号：US14882784
申请日：2015-10-14
发明人： Gi-Moon Hong , Suhwan Kim , Deog-Kyoon Jeong
CPC分类号： H04L7/0079 , H03L7/0812 , H03L7/087 , H03L7/0891 , H03L7/0896 , H04L7/0008 , H04L7/0012 , H04L7/0037 , H04L7/02 , H04L7/0337 , H04L7/04
摘要： A data receiver includes a sampling clock generator configured to generate a sampling clock signal from an internal clock signal according to a data strobe signal, and a sampler configured to sample a data signal according to the sampling clock signal.
摘要翻译： 数据接收机包括：采样时钟发生器，被配置为根据数据选通信号从内部时钟信号产生采样时钟信号;以及采样器，被配置为根据采样时钟信号对数据信号进行采样。
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公开(公告)号：US20160164667A1
公开(公告)日：2016-06-09
申请号：US14666537
申请日：2015-03-24
申请人： SK hynix Inc.
发明人： Hyun Bae LEE
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0891 , H03L7/0896 , H04L5/0053 , H04L7/0337
摘要： A clock and data recovery circuit may include: a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing a clock signal and data; a filtering unit configured to generate an up signal and a down signal based on a number of generation times of the early phase detection signal and a number of generation times of the late phase detection signal; a phase information summing unit configured to receive an output of the filtering unit at each cycle of the clock signal, and generate first and second phase control signals by summing up numbers of the up signals and the down signals received from the filtering unit during a summing-up time; and a phase interpolator configured to adjust a phase of the clock signal according to the first and second phase control signals.
摘要翻译： 时钟和数据恢复电路可以包括：相位检测单元，被配置为通过比较时钟信号和数据来产生早期相位检测信号和后期相位检测信号; 滤波单元，被配置为基于早期相位检测信号的生成次数和后期相位检测信号的生成次数生成上升信号和下降信号; 相位信息求和单元，被配置为在所述时钟信号的每个周期接收所述滤波单元的输出，并且在求和期间通过对所述上升信号的数量和从所述滤波单元接收的所述下降信号进行相加来生成第一和第二相位控制信号 - 时间 以及相位插值器，被配置为根据第一和第二相位控制信号调整时钟信号的相位。
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公开(公告)号：US20160099638A1
公开(公告)日：2016-04-07
申请号：US14874315
申请日：2015-10-02
申请人： NXP B.V.
CPC分类号： H02M3/07 , H02M3/073 , H03L7/0896 , H04R3/00 , H04R19/04
摘要： A differential dynamic charge pump circuit comprising; a first charging stage in series with a second charging stage; the first charging stage comprising a first circuit input for receiving an alternating clock signal; a second circuit input for receiving an inverted version of the alternating clock signal; a first output inverter arrangement configured to receive output voltages from upper and lower charge pump arrangements and having a first output and a second output for providing a dynamic differential output; the second charging stage comprising a first input and a second input configured to receive the output signal from the first stage; a second output inverter arrangement configured to receive output voltages from upper and lower charge pump arrangements and having a first output and a second output for providing a dynamic differential output of the circuit.
摘要翻译： 一种差分动态电荷泵电路，包括： 与第二充电阶段串联的第一充电阶段; 所述第一充电阶段包括用于接收交替时钟信号的第一电路输入; 用于接收所述交替时钟信号的反相版本的第二电路输入; 第一输出反相器装置，被配置为接收来自上部和下部电荷泵装置的输出电压，并且具有用于提供动态差分输出的第一输出和第二输出; 所述第二充电阶段包括被配置为从所述第一级接收所述输出信号的第一输入和第二输入; 第二输出反相器装置，被配置为接收来自上电荷泵装置和下电荷泵装置的输出电压，并具有第一输出端和第二输出端，用于提供电路的动态差分输出。
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公开(公告)号：US09257899B1
公开(公告)日：2016-02-09
申请号：US14490853
申请日：2014-09-19
发明人： Yi-Lung Chen
CPC分类号： H03L7/093 , H03L7/0896
摘要： A charge pump circuit and a phase lock loop circuit (PLL) having the same are provided. A main voltage divider and an assistant voltage divider configured in the charge pump circuit generate a voltage division within a predetermined time of activating the charge pump circuit. Therefore, when the charge pump circuit initiates operating, a voltage of a control end of a main switch set configured in the charge pump circuit is set to be the voltage division. The voltage of the control end is gradually decreased from the voltage division to a stable voltage according to a first current and a second current flowing through the main switch set. Accordingly, it can decrease the time from initiating operation of the pump circuit to stabilizing the voltage of the control end, thereby it can increase the working efficiency of the PLL.
摘要翻译： 提供了一种电荷泵电路和具有该电荷泵电路的锁相环电路（PLL）。 配置在电荷泵电路中的主分压器和辅助分压器在激活电荷泵电路的预定时间内产生电压分配。 因此，当电荷泵电路开始工作时，将配置在电荷泵电路中的主开关组的控制端的电压设定为分压。 根据流过主开关组的第一电流和第二电流，控制端的电压从分压逐渐减小到稳定的电压。 因此，可以减少从启动泵电路运行到稳定控制端的电压的时间，从而可以提高PLL的工作效率。
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公开(公告)号：US20140340133A1
公开(公告)日：2014-11-20
申请号：US14276567
申请日：2014-05-13
IPC分类号： H03K19/003 , H03L7/08
CPC分类号： H03K19/0033 , G11C5/005 , H03K3/0375 , H03K3/356121 , H03L7/08 , H03L7/0891 , H03L7/0896 , H03L7/095 , H03L7/18
摘要： A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.
摘要翻译： 一种包括数据存储元件的电路; 第一和第二输入电路分别耦合到数据存储元件的第一和第二输入端，并且每个输入电路包括适于产生分别提供给第一和第二输入的第一和第二输入信号作为初始信号的函数的多个分量; 其中所述数据存储元件包括第一存储节点，并且被配置为使得通过由第一晶体管的导通状态来确定存储在所述第一存储节点处的电压状态以防止所述第一和第二输入信号中仅一个的变化 耦合到所述第一存储节点并且基于所述第一输入信号以及耦合到所述第一存储节点的第二晶体管的导通状态并基于所述第二输入信号进行控制。
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公开(公告)号：US08829962B2
公开(公告)日：2014-09-09
申请号：US14177582
申请日：2014-02-11
申请人： Ning Zhu , Hajime Shibata
发明人： Ning Zhu , Hajime Shibata
IPC分类号： H03L7/06
CPC分类号： H02M3/06 , H03L7/0814 , H03L7/0893 , H03L7/0896 , H03L7/0898
摘要： A delay locked loop (DLL) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (PFD) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal.
摘要翻译： 延迟锁定环（DLL）包括延迟时钟信号以产生延迟的时钟信号的延迟线，用于检测时钟信号和延迟时钟信号之间的相位和/或频率差的相位频率检测器（PFD），以及 具有可调偏置电流的电荷泵，用于将考虑到将偏置电流调节转换为控制电压的相位和/或频率差，其中控制电压控制延迟的时钟信号的延迟量。
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17.发明授权公开(公告)号：US08664985B2
公开(公告)日：2014-03-04
申请号：US13548079
申请日：2012-07-12
申请人： Yu-Li Hsueh , Jing-Hong Conan Zhan
发明人： Yu-Li Hsueh , Jing-Hong Conan Zhan
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0891 , H03L7/0896 , H03L7/1072
摘要： The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.
摘要翻译： 本发明提供了一种解决方案，通过各种电路配置通过各种电路配置升级相位频率检测器（PFD）和电荷泵（CP）增益，提供令人满意的性能，而不需要锁相环（PLL）电路的显着占地面积， 采用一个或多个触发器，延迟元件和高级电路技术。
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公开(公告)号：US20130265104A1
公开(公告)日：2013-10-10
申请号：US13792242
申请日：2013-03-11
IPC分类号： H02M3/00
CPC分类号： H02M3/00 , H03L7/0896
摘要： A circuit includes an output node; a first current source coupled via at least one first switch to at least the output node and a calibration node, wherein the first switch alternately operably couples the first current source to the output node or the calibration node; a second current source of opposing polarity to the first current source and operably coupled via at least one second switch to at least the output node and the calibration node, wherein the second switch alternately operably couples the second current source to the output node or the calibration node; and a current control circuit having an adjustment circuit operably coupled to the calibration node, wherein the current control circuit couples both the first and second current sources to the calibration node when a current from the first/second current source is not to be used as an output from the output node.
摘要翻译： 电路包括输出节点; 经由至少一个第一开关耦合到至少所述输出节点的第一电流源和校准节点，其中所述第一开关交替地可操作地将所述第一电流源耦合到所述输出节点或所述校准节点; 与所述第一电流源相反的极性的第二电流源，并且经由至少一个第二开关可操作地耦合到至少所述输出节点和所述校准节点，其中所述第二开关交替地可操作地将所述第二电流源耦合到所述输出节点或所述校准 节点; 以及电流控制电路，其具有可操作地耦合到所述校准节点的调节电路，其中当来自所述第一/第二电流源的电流不被用作所述校准节点时，所述电流控制电路将所述第一和第二电流源耦合到所述校准节点 从输出节点输出。
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公开(公告)号：US08525564B2
公开(公告)日：2013-09-03
申请号：US13278003
申请日：2011-10-20
IPC分类号： H03L7/06
CPC分类号： H03L7/0896 , H03L7/0895
摘要： Charge-based charge pumps are described which include a switchable capacitor configured for connection to a voltage source, a ground, and a charge pump output. A first pair of switches include a first switch configured to connect the switchable capacitor to ground and a second switch configured to connect the switchable capacitor to the voltage source. A second pair of switches include a third switch configured to connect a first node, between the switchable capacitor and ground, to the charge pump output, and a fourth switch configured to connect a second node, between the switchable capacitor and the voltage source, to the charge pump output. Locked loop designs, such as phase locked loops or delay locked loops, are described that include charge-based charge pumps.
摘要翻译： 描述了基于充电的电荷泵，其包括被配置为连接到电压源，接地和电荷泵输出的可切换电容器。 第一对开关包括被配置为将可切换电容器接地的第一开关和被配置为将可切换电容器连接到电压源的第二开关。 第二对开关包括第三开关，其被配置为将可切换电容器和地之间的第一节点连接到电荷泵输出;以及第四开关，被配置为将可切换电容器和电压源之间的第二节点连接到 电荷泵输出。 描述了锁定环设计，例如锁相环或延迟锁定环，其包括基于电荷的电荷泵。
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公开(公告)号：US08400199B2
公开(公告)日：2013-03-19
申请号：US13095873
申请日：2011-04-28
申请人： Yu-Li Hsueh , Yi-Hsien Cho , Jing-Hong Conan Zhan
发明人： Yu-Li Hsueh , Yi-Hsien Cho , Jing-Hong Conan Zhan
IPC分类号： H03L7/06
CPC分类号： H03L5/00 , H03L7/089 , H03L7/0895 , H03L7/0896 , H03L7/093
摘要： A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.
摘要翻译： 电荷泵设置在相位锁定系统中。 电荷泵包括源元件，排液元件和偏移元件。 源极元件被布置成根据第一控制信号选择性地将第一电流源流到电荷泵的输出端，并且排水元件被布置成根据第二控制信号从输出端选择性地排出第二电流。 偏移元件布置成根据第三控制信号经由输出端选择性地导通偏移电流，并且当锁相系统处于锁相状态时，源元件和排液元件之一被禁用。
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