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1078 条记录 (耗时 0.032 秒)

    LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME
    11.
    发明申请
    LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME 有权

    公开(公告)号：US20230123956A1

    公开(公告)日：2023-04-20

    申请号：US18068666

    申请日：2022-12-20

    申请人： NVIDIA Corporation

    发明人： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

    IPC分类号： G06F11/267 ,  G06F11/22 ,  G06F1/3296 ,  G06F11/273 ,  G06F11/27

    摘要： In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

    REDUCED SIGNALING INTERFACE METHOD & APPARATUS
    12.
    发明申请
    REDUCED SIGNALING INTERFACE METHOD & APPARATUS 有权

    公开(公告)号：US20230058458A1

    公开(公告)日：2023-02-23

    申请号：US17982010

    申请日：2022-11-07

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/267 ,  G01R31/3177

    摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

    MACHINE LEARNING FOR TAPS TO ACCELERATE TDECQ AND OTHER MEASUREMENTS
    13.
    发明申请
    MACHINE LEARNING FOR TAPS TO ACCELERATE TDECQ AND OTHER MEASUREMENTS 有权

    公开(公告)号：US20230050162A1

    公开(公告)日：2023-02-16

    申请号：US17876817

    申请日：2022-07-29

    申请人： Tektronix, Inc.

    发明人： Kan Tan ,  John J. Pickerd

    IPC分类号： G06F11/273 ,  G06F11/267

    摘要： A test and measurement instrument has an input configured to receive a signal from a device under test, a memory, a user interface to allow the user to input settings for the test and measurement instrument, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to: acquire a waveform representing the signal received from the device under test; generate one or more tensor arrays based on the waveform; apply machine learning to the one or more tensor arrays to produce equalizer tap values; and apply equalization to the waveform using the equalizer tap values to produce an equalized waveform; and perform a measurement on the equalized waveform to produce a value related to a performance requirement for the device under test. A method of testing a device under test includes acquiring a waveform representing a signal received from the device under test, generating one or more tensor arrays based on the waveform, applying machine learning to the one or more tensor arrays to produce equalizer tap values, applying the equalizer taps values to the waveform to produce an equalized waveform, performing a measurement on the equalized waveform to produce a value related to a performance requirement for the device under test.

    Leveraging low power states for fault testing of processing cores at runtime
    14.
    发明授权
    Leveraging low power states for fault testing of processing cores at runtime 有权

    公开(公告)号：US11573872B2

    公开(公告)日：2023-02-07

    申请号：US17556473

    申请日：2021-12-20

    申请人： NVIDIA Corporation

    发明人： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

    IPC分类号： G06F11/267 ,  G06F11/22 ,  G06F11/273 ,  G06F11/27 ,  G06F1/3296

    摘要： In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

    JTAG bus communication method and apparatus
    15.
    发明授权
    JTAG bus communication method and apparatus 有权

    公开(公告)号：US11549982B2

    公开(公告)日：2023-01-10

    申请号：US17213808

    申请日：2021-03-26

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G01R31/3177

    摘要： The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

    Automated functional testing systems and methods of making and using the same
    16.
    发明授权
    Automated functional testing systems and methods of making and using the same 有权

    公开(公告)号：US11543328B2

    公开(公告)日：2023-01-03

    申请号：US16629570

    申请日：2018-04-06

    申请人： CVE Technology Group, Inc.

    发明人： Myung Ki Kim

    IPC分类号： G01M99/00 ,  G01R31/28 ,  G06F11/273 ,  G10K11/16 ,  G10L25/51 ,  H04R29/00 ,  B65G61/00 ,  G06F3/041 ,  H04N17/00 ,  B25J9/16 ,  G06F11/263 ,  G06F11/267 ,  G01L25/00 ,  G03B43/00

    摘要： An automatic robot control system and methods relating thereto are described. These systems include components such as a touch screen panel (“TSP”) robot controller for controlling a TSP robot, a camera robot controller for controlling a camera robot and an audio robot controller for controlling an audio robot. The TSP robot operates inside a TSP testing subsystem, the camera robot operates inside a camera testing subsystem, and the audio robot operates inside an audio testing subsystem. Inside the audio testing subsystem, an audio signals measurement system, using a bi-directional coupling, controls the operation of the audio robot controller. In this control scheme, a test application controller is designed to control the different types of subsystem robots. Methods relating to TSP, camera, and audio robots, and their controllers, taken individually or in combination, for automatic testing of device functionalities are also described.

    SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
    18.
    发明申请
    SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT 有权

    公开(公告)号：US20220146574A1

    公开(公告)日：2022-05-12

    申请号：US17579629

    申请日：2022-01-20

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/317 ,  G06F11/27 ,  G01R31/3185 ,  G01R31/3177 ,  G06F11/267

    摘要： An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.