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    INTEGRATED CIRCUIT WITH ASYMMETRIC ARRANGEMENTS OF MEMORY ARRAYS
    2.
    发明公开
    INTEGRATED CIRCUIT WITH ASYMMETRIC ARRANGEMENTS OF MEMORY ARRAYS 审中-公开

    公开(公告)号：US20230290395A1

    公开(公告)日：2023-09-14

    申请号：US18319969

    申请日：2023-05-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC CHINA COMPANY LIMITED

    Inventor： Xiu-Li YANG ,  He-Zhou WAN ,  Kuan CHENG ,  Ching-Wei WU

    IPC: G11C8/10 ,  G11C8/12 ,  G11C8/14

    CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C8/14

    Abstract: An integrated circuit includes integrated circuit includes a memory bank, a first group of word lines, a second group of word lines, an access circuit, a converter circuit and a decoder circuit. The first group of word lines is coupled to the memory bank. The second group of word lines is coupled to the memory bank, and arranged in order with the first group of word lines. The access circuit is configured to read the memory bank. The converter circuit is configured to control the access circuit at least based on a first control signal. The decoder circuit is configured to generate the first control signal at least according to a first bit and a second bit of an address signal. The first bit and the second bit indicates one group of the first group of word lines and the second group of word lines.

    INTEGRATED CIRCUIT
    3.
    发明申请
    INTEGRATED CIRCUIT 有权

    公开(公告)号：US20210201972A1

    公开(公告)日：2021-07-01

    申请号：US16794104

    申请日：2020-02-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC CHINA COMPANY LIMITED

    Inventor： Xiu-Li YANG ,  He-Zhou WAN ,  Kuan CHENG ,  Ching-Wei WU

    IPC: G11C8/10 ,  G11C8/14 ,  G11C8/12

    Abstract: An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of complementary data lines. The first pair of complementary data lines extend along the first array of memory cells, and are coupled to the first array of memory cells. The second pair of complementary data lines extend along the second array of memory cells, and are coupled to the first pair of complementary data lines. The third pair of complementary data lines extend along the second array of memory cells, and are coupled to the second array of memory cells. A number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells.

    INTEGRATED CIRCUIT WITH ASYMMETRIC ARRANGEMENTS OF MEMORY ARRAYS
    6.
    发明申请
    INTEGRATED CIRCUIT WITH ASYMMETRIC ARRANGEMENTS OF MEMORY ARRAYS 有权

    公开(公告)号：US20220215867A1

    公开(公告)日：2022-07-07

    申请号：US17704606

    申请日：2022-03-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC CHINA COMPANY LIMITED

    Inventor： Xiu-Li YANG ,  He-Zhou WAN ,  Kuan CHENG ,  Ching-Wei WU

    IPC: G11C8/10 ,  G11C8/14 ,  G11C8/12

    Abstract: An integrated circuit includes multiple memory cells, a first pair of complementary data lines, a second pair of complementary data lines, multiple first word lines, and multiple second word lines. The memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are coupled to the second array of memory cells. Lengths of the first pair of complementary data lines are shorter than lengths of the second pair of complementary data lines. The first word lines and the second word lines are arranged according to a predetermined ratio of a number of the first word lines to a number of the second word lines. The predetermined ratio is less than 1.

    METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED COUPLING CAPACITOR
    9.
    发明申请
    METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED COUPLING CAPACITOR 有权
    用金属化耦合电容器形成集成电路的方法和装置

    公开(公告)号：US20150076575A1

    公开(公告)日：2015-03-19

    申请号：US14031057

    申请日：2013-09-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ching-Wei WU ,  Wei-Shuo KAO ,  Chia-Cheng CHEN ,  Kuang Ting CHEN

    IPC: H01L27/11 ,  H01L29/94

    CPC classification number: H01L27/1116 ,  G11C7/12 ,  G11C7/18 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/005 ,  H01L29/94

    Abstract: An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line.

    Abstract translation: 一种集成电路包括设置在第一金属层中并沿第一方向延伸的存储单元阵列的位单元的多个金属层，所述存储单元阵列的多个字线设置在第二金属层中并在 与第一方向不同的第二方向，以及布置在基本上彼此相邻并且至少部分地跨过存储单元阵列延伸的第三金属层中的至少两个导电迹线，所述至少两个导电迹线中的第一导电迹线耦合到 写辅助电路的驱动源节点和耦合到写辅助电路的使能输入的至少两个导电迹线的第二导电迹线，其中所述至少两个导电迹线形成至少一个嵌入式电容器，其具有电容 耦合到位线。

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