公开(公告)号：US11729915B1

公开(公告)日：2023-08-15

申请号：US17700657

申请日：2022-03-22

申请人： TactoTek Oy

发明人： Tomi Simula ,  Tapio Rautio

IPC分类号： H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/22 ,  H05K3/28 ,  H05K3/34 ,  H05K3/46 ,  H01L21/00 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L21/66 ,  H01L21/78 ,  H01L21/673 ,  H01L23/00 ,  H01L23/02 ,  H01L23/04 ,  H01L23/28 ,  H01L23/48 ,  H01L23/49 ,  H01L23/52 ,  H01L23/488 ,  H01L23/495 ,  H01L23/498 ,  H01L23/552 ,  H05K1/03 ,  H05K1/11 ,  H05K3/12

CPC分类号： H05K3/284 ,  H05K1/0393 ,  H05K1/111 ,  H05K3/0067 ,  H05K3/1283 ,  H05K2203/1316 ,  H05K2203/1322

摘要： The method for manufacturing a number of electrical nodes, wherein the method includes providing a number of electronic circuits onto a first substrate, such as on a printed circuit board or other electronics substrate, optionally, a low-temperature co-fired ceramic substrate, wherein each one of the electronic circuits includes a circuit pattern and at least one electronics component in connection with the circuit pattern, wherein the electronic circuits are spaced from each other on the first substrate, thereby defining a blank area surrounding each one of the number of electronic circuits, respectively, and providing potting or casting material to embed each one of the number of electronic circuits in the potting or casting material, and, subsequently, hardening, optionally including curing, the potting or casting material to form a filler material layer of the number of electrical nodes.

公开(公告)号：US20230120152A1

公开(公告)日：2023-04-20

申请号：US17896637

申请日：2022-08-26

申请人： FUJI ELECTRIC CO., LTD.

发明人： Yuma MURATA ,  Ryoichi KATO ,  Shinji TADA

IPC分类号： H01L23/538 ,  H01L23/02 ,  H01L23/66 ,  H01L23/498

摘要： A semiconductor module includes a first case having a first side face, a first insulating paper disposed on the first case and having a first width in a first direction and having a notch with a second width smaller than the first width, a first terminal between the first case and the first insulating paper, having an exposed portion exposed from the first insulating paper at an area where the notch is formed, and a second terminal on the first insulating paper at a side opposite to a side where the first terminal is disposed. The first terminal and the first insulating paper have extended portions extending to an outside of the first case from the first side face so that a portion of the first insulating paper where the notch is formed and the exposed portion of the first terminal are located at the outside of the first case.

公开(公告)号：US20220415734A1

公开(公告)日：2022-12-29

申请号：US17806253

申请日：2022-06-09

申请人： INVENSAS BONDING TECHNOLOGIES, INC.

发明人： Rajesh Katkar ,  Liang Wang ,  Cyprian Emeka Uzoh ,  Shaowu Huang ,  Guilian Gao ,  Ilyas Mohammed

IPC分类号： H01L23/10 ,  B81C1/00 ,  B81B7/00 ,  H01L23/04 ,  H01L23/053 ,  H01L23/02

摘要： Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

公开(公告)号：US11538735B2

公开(公告)日：2022-12-27

申请号：US16529023

申请日：2019-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Rong Chun ,  Kuo Lung Pan ,  Pei-Hsuan Lee ,  Chien Ling Hwang ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC分类号： H01L23/02 ,  H01L21/44 ,  H01L21/48 ,  H01L23/40 ,  H01L23/00

摘要： In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

公开(公告)号：US20220367522A1

公开(公告)日：2022-11-17

申请号：US17844590

申请日：2022-06-20

申请人： pSemi Corporation

发明人： Simon Edward Willard

IPC分类号： H01L27/12 ,  H01L23/02 ,  H03K17/687

摘要： Electronic circuits and methods encompassing an RF switch comprising a plurality of series-coupled (stacked) integrated circuit (IC) SOI MOSFETs having a distributed back-bias network structure comprising groups of substrate contacts coupled to a bias voltage source through a resistive ladder. The distributed back-bias network structure sets the common IC substrate voltage at a fixed DC bias but resistively decouples groups of MOSFETs with respect to RF voltages so that the voltage division characteristics of the MOSFET stack are maintained. The distributed back-bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET is effective as a switch device, while mitigating loss, leakage, crosstalk, and distortion. RF switches in accordance with the present invention are particularly useful as antenna switches.

公开(公告)号：US11476125B2

公开(公告)日：2022-10-18

申请号：US16865953

申请日：2020-05-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei Sen Chang ,  Yu-Feng Chen ,  Chen-Shien Chen ,  Mirng-Ji Lii

IPC分类号： H01L23/34 ,  H01L23/02 ,  H01L21/66 ,  H01L21/48 ,  H01L25/18 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

摘要： A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer.

公开(公告)号：US11437297B2

公开(公告)日：2022-09-06

申请号：US17255415

申请日：2018-09-28

申请人： Intel Corporation

发明人： Guoliang Ying ,  Jun Lu ,  Guangying Zhang ,  Xinglong Xu ,  Wei Liao ,  Fangbo Zhu

IPC分类号： H01L23/40 ,  H01L23/02 ,  H01L23/00 ,  H01L21/50 ,  H01L23/367

摘要： Systems, apparatuses, processes, and techniques are provided which are related to a vapor chamber (750) having a first side and a second side opposite the first side, where the first side is to thermally couple to a heat sink (708) and the second side to thermally couple to a heat source. The vapor chamber (750) may include a compressible mechanism disposed within the vapor chamber (750) coupled with the first side and the second side where the second side, when coupled to the heat source, is to deform at least partially to match a shape of the heat source. The compressible mechanism within the vapor chamber (750) may moderate the deformation of the second side.

公开(公告)号：US20220238418A1

公开(公告)日：2022-07-28

申请号：US17562965

申请日：2021-12-27

申请人： ABLIC Inc.

发明人： Koji TSUKAGOSHI

IPC分类号： H01L23/495 ,  H01L23/532 ,  H01L23/02 ,  H01L21/56 ,  H01L23/00

摘要： The present invention provides a small and thin semiconductor device. The semiconductor device flip-chip bonds a semiconductor chip 1 and a lead 6 via a metal bonding portion 5 and includes a sealing resin covering them. The metal bonding portion 5 is provided with a gold-rich bonding layer 5a on the side of a first electrode 3a of the semiconductor chip 1 and a gold-rich bonding layer 5b on the side of a second electrode 3b of the lead 6, and connection between the semiconductor chip 1 and the lead 6 is strengthened, so that the semiconductor device does not require an anchor portion.

公开(公告)号：US20220192042A1

公开(公告)日：2022-06-16

申请号：US17120958

申请日：2020-12-14

申请人： Intel Corporation

发明人： Mohammad Enamul Kabir ,  Adel A. Elsherbini ,  Manish Chandhok

IPC分类号： H05K5/06 ,  H01L23/02 ,  H01L23/00 ,  B81B7/00 ,  H01L25/065 ,  H01L23/538

摘要： Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.

公开(公告)号：US11289389B2

公开(公告)日：2022-03-29

申请号：US16462157

申请日：2018-11-01

申请人： WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.

发明人： Si Xie

IPC分类号： H01L23/02 ,  H01L23/13 ,  G02F1/1333 ,  G09F9/33

摘要： A display panel is provided. The display panel includes a display component and a chip, wherein the display component includes at least one recess portion and a gate line layer, and the gate line layer is exposed on a bottom surface of the recess portion. The chip is connected to the display component, and at least one portion of the chip is embedded in the recess portion. The present disclosure can prevent a display component in the display panel from being in contact with a chip due to bending of the display panel.