公开(公告)号：US07640482B2

公开(公告)日：2009-12-29

申请号：US11470982

申请日：2006-09-07

Applicant: Laurent Paumier ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Vincent Heinrich

IPC: G11C29/00

CPC classification number: H03M13/152 ,  H03M13/1105 ,  H03M13/1137 ,  H03M13/13 ,  H03M13/2963 ,  H03M13/6516 ,  H03M13/6566

Abstract: A device for storing blocks of bits intended to be decoded according to a block decoding algorithm. The blocks are likely to belong to a given category out of a first category and a second category. The first category corresponds to a first given block size, and the second category corresponds to at least one second given block size less than said first block size. The storage device comprises three storage elements having a size suitable for storing one block of the first category each, and at least two of which are structured to store either one block of the first category, or one block of the second category or a number of blocks of the second category simultaneously.

Abstract translation: 一种用于根据块解码算法存储要被解码的位的块的装置。 块可能属于第一类别和第二类别中的给定类别。 第一类别对应于第一给定块大小，并且第二类别对应于小于所述第一块大小的至少一个第二给定块大小。 存储设备包括三个存储元件，其具有适合于存储每个第一类别的一个块的尺寸，并且其中的至少两个被构造为存储第一类别的一个块或第二类别的一个块或多个 同时第二类块。

公开(公告)号：US07639924B2

公开(公告)日：2009-12-29

申请号：US10741812

申请日：2003-12-19

Applicant: Frederic Roelens

Inventor： Frederic Roelens

IPC: H04N7/00

CPC classification number: H04N21/4392 ,  H04N21/4147 ,  H04N21/42661 ,  H04N21/4305 ,  H04N21/4325 ,  H04N21/44004

Abstract: A method and device are provided for decoding one or more audio data streams and one or more video data streams obtained from one or more sources. According to the method, portions of the audio data stream and portions of the video data stream are loaded into a set of buffer memories, and audio data and video data are supplied from the buffer memories at the input of at least one audio decoder and of at least one video decoder, respectively. The video data and the audio data are decoded with the aid of the audio decoder and of the video decoder, respectively. The loading is carried out by a management module according to the Pull mode. Alternately or additionally, the supplying is carried out by the management module according to the Push mode. The management module is regulated by the video decoder.

Abstract translation: 提供了一种方法和装置，用于对一个或多个音频数据流和从一个或多个源获得的一个或多个视频数据流进行解码。 根据该方法，音频数据流的一部分和视频数据流的一部分被加载到一组缓冲存储器中，并且在至少一个音频解码器的输入端从缓冲存储器提供音频数据和视频数据，并且 至少一个视频解码器。 借助于音频解码器和视频解码器，分别对视频数据和音频数据进行解码。 根据拉模式，管理模块进行加载。 或者或另外，由管理模块根据推送模式进行供应。 管理模块由视频解码器调节。

公开(公告)号：US20090310319A1

公开(公告)日：2009-12-17

申请号：US12543873

申请日：2009-08-19

Applicant: PIERRE BORMANN ,  Luc Morineau ,  Jacques Chavade

Inventor： PIERRE BORMANN ,  Luc Morineau ,  Jacques Chavade

IPC: H05K7/12

CPC classification number: H01L23/49838 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/10734

Abstract: A device is provided for electrically connecting an integrated circuit chip. The device includes a main board, an intermediate board, and electrical connection balls in a space separating the boards. In the space, a peripheral zone comprises a peripheral matrix of balls, a central zone comprises a central matrix of balls, a first secondary zone comprises a matrix of electrical connection vias linked to the balls of the two adjacent rows of balls of the peripheral matrix, and a second secondary zone comprises a matrix of electrical connection vias linked to balls of the central matrix. The first secondary zone and the second secondary zone are separated by an intermediate zone that includes at least a first part having at least one complementary row of electrical connection balls, and a second part having complementary electrical connection vias linked to the balls of this complementary row.

Abstract translation: 提供一种用于电连接集成电路芯片的装置。 该装置包括主板，中间板和分隔板的空间中的电连接球。 在该空间中，周边区域包括球的外围矩阵，中心区域包括球的中心矩阵，第一次级区域包括连接到外围矩阵的两个相邻行球的球的电连接通孔矩阵 ，并且第二次级区域包括连接到中心矩阵的球的电连接通孔矩阵。 第一次级区域和第二次级区域由包括至少一个具有至少一个互补排的电连接球的第一部分的中间区隔开，以及具有互补电连接通路的第二部分，该互补电连接通孔连接到该互补排的球 。

公开(公告)号：US07629186B2

公开(公告)日：2009-12-08

申请号：US11392130

申请日：2006-03-29

Applicant: Jean-Louis Siaudeau

Inventor： Jean-Louis Siaudeau

IPC: H01L21/66 ,  G01R31/26 ,  H01L23/58 ,  H01L23/544

CPC classification number: H01L21/681 ,  H01L21/67259 ,  H01L21/67282 ,  H01L21/68 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and a system of alignment of an integrated circuit chip pick-and-place equipment with an origin of a wafer supporting these circuits, comprising optically searching on the wafer at least one reference pattern formed, on manufacturing of the integrated circuits, in a reference chip, the reference pattern being different from optically-recognizable patterns of the other chips.

Abstract translation: 一种集成电路芯片拾取和放置设备与支撑这些电路的晶片的原点的对准方法和系统，包括：在制造集成电路时，在晶圆上将形成的至少一个参考图案光学搜索到 参考芯片，参考图案不同于其他芯片的光学可识别图案。

公开(公告)号：US07605495B2

公开(公告)日：2009-10-20

申请号：US11244423

申请日：2005-10-05

Applicant: Raynald Achart

Inventor： Raynald Achart

IPC: G05F1/577

CPC classification number: H02M1/10 ,  H02M7/06 ,  Y10T307/281

Abstract: A circuit intended to provide two D.C. voltages of inverted polarities based on an A.C. voltage, comprising: two capacitors having their respective electrodes connected to two terminals intended to receive said A.C. voltage and having their second respective electrodes connected to each other by two first diodes in anti-series; a controllable current source having a first terminal connected to the common anodes of said first diodes; two second diodes connected in anti-series between said terminals intended to receive said A.C. voltage and having their common cathodes connected to a second terminal of said controllable current source; a circuit for controlling said current source; and two third diodes connected in anti-series between said terminals intended to receive said A.C. voltage, said control circuit sampling its power supply between the common cathodes of the second diodes and the common anodes of the third ones.

Abstract translation: 一种旨在基于AC电压提供反向极性的两个DC电压的电路，包括：两个电容器，其各自的电极连接到两个用于接收所述AC电压的端子，并且其第二相应电极通过两个第一二极管彼此连接 反系列; 可控电流源，其具有连接到所述第一二极管的共阳极的第一端子; 两个二极管连接在所述端子之间的反串联中，用于接收所述交流电压，并使它们的共阴极连接到所述可控电流源的第二端; 用于控制所述电流源的电路; 以及两个连接在所述端子之间的反串联的第二二极管，用于接收所述交流电压，所述控制电路对第二二极管的公共阴极和第三二极管的公共阳极之间的电源进行采样。

公开(公告)号：US07581132B2

公开(公告)日：2009-08-25

申请号：US11219345

申请日：2005-09-01

Applicant: Olivier Plourde

Inventor： Olivier Plourde

IPC: G06F1/00 ,  G06F1/04

CPC classification number: G06F1/08

Abstract: A method is provided for configuring a microcontroller clock system that includes a main oscillator, a phase locked loop, and a backup oscillator. According to the method, the main oscillator and the backup oscillator are activated in reset mode. A clock signal is generated from the backup oscillator, and the clock signal that is generated is applied to the microcontroller in order to start the microcontroller. Also provided are a clock system for a microcontroller, and a microcontroller including a clock system.

Abstract translation: 提供了一种用于配置包括主振荡器，锁相环和备用振荡器的微控制器时钟系统的方法。 根据该方法，主振荡器和备用振荡器在复位模式下被激活。 从备用振荡器产生时钟信号，生成的时钟信号被施加到微控制器以启动微控制器。 还提供了用于微控制器的时钟系统和包括时钟系统的微控制器。

公开(公告)号：US07577886B2

公开(公告)日：2009-08-18

申请号：US11484355

申请日：2006-07-10

Applicant: Frédéric Bancel ,  David Hely

Inventor： Frédéric Bancel ,  David Hely

IPC: G01R31/28

CPC classification number: G01R31/31719 ,  G01R31/318533

Abstract: An electronic circuit comprises a plurality of configurable cells configured according to a chaining command signal. These configurable cells are configured either in a chained state in which the configurable cells are functionally connected in a chain to form a shift register, if the chaining command signal is in a first state, or in a functional state in which the configurable cells are functionally linked to logic cells with which they co-operate to form at least one logic circuit, if the mode command signal is in a second state. It is provided that a test data word will be preceded by a signature. The set formed by the digital signature and the data word forms a test sequence. The signature is verified before the introduction of the test data word by an appropriate detection circuit.

Abstract translation: 电子电路包括根据链接命令信号配置的多个可配置单元。 这些可配置单元被配置为链状态，其中可配置单元在链中功能性连接以形成移位寄存器，如果链接命令信号处于第一状态，或处于功能状态，其中可配置单元在功能上 如果模式命令信号处于第二状态，则它们与它们协作以形成至少一个逻辑电路的逻辑单元相连。 提供测试数据字将在其前面加上签名。 由数字签名和数据字形成的集合形成一个测试序列。 在通过适当的检测电路引入测试数据字之前验证签名。

公开(公告)号：US20090192939A1

公开(公告)日：2009-07-30

申请号：US12361636

申请日：2009-01-29

Applicant: Ennio Salemi

Inventor： Ennio Salemi

IPC: G06Q40/00

CPC classification number: H04L47/10 ,  G06Q20/40 ,  H04L47/17 ,  H04L47/39

Abstract: The method of transferring data between a first and a second set of elements via a switch that includes a set of paths each associated with a weighting coefficient representing a data stream for each path. The method includes a credit flow control between the first set of elements and the switch and a credit flow control between the switch and the second set of elements. An available credit coefficient is computed for each element of the first set on the basis of a credit allocated by each element of the second set and of the weighting coefficient of each path.

Abstract translation: 一种通过交换机在第一和第二组元素之间传送数据的方法，该交换机包括一组路径，每一路径与表示每个路径的数据流的加权系数相关联。 该方法包括在第一组元件和开关之间的信用流量控制和开关与第二组元件之间的信用流量控制。 基于由第二集合的每个元素分配的信用和每个路径的加权系数来计算第一集合的每个元素的可用信用系数。

公开(公告)号：US07555001B2

公开(公告)日：2009-06-30

申请号：US11157562

申请日：2005-06-21

Applicant: Marcello Coppola ,  Riccardo Locatelli ,  Giuseppe Maruccia ,  Lorenzo Pieralisi

Inventor： Marcello Coppola ,  Riccardo Locatelli ,  Giuseppe Maruccia ,  Lorenzo Pieralisi

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04L12/42

Abstract: A system for routing a data packet between N elements includes N network interfaces respectively connected to the N elements, with N being an even integer, and an on-chip packet-switched communication network arranged in a ring structure. The packet-switched communication network includes N routers respectively connected to the N interfaces, and N pairs of opposite uni-directional ring links. Each pair of ring links couples two adjacent routers in the ring structure, and each ring link provides two virtual channels. There are N/2 pairs of opposite uni-directional crossing links, with each pair of crossing links coupling two diametrically opposite routers in the ring structure. Processing circuitry is distributed within the N routers and the N network interfaces for determining direction of the data packet to be transmitted over a path from a source element to a destination element in the ring structure, and for determining at each router in the path which virtual channel is to be used to avoid deadlocks in the transmission.

Abstract translation: 用于在N个元素之间路由数据分组的系统包括分别连接到N个元素的N个网络接口，N是偶数整数，以及以环形结构排列的片上分组交换通信网络。 分组交换通信网络包括分别连接到N个接口的N个路由器和N个相对的单向环形链路。 每对环形链路将环形结构中的两个相邻路由器耦合，并且每个环形链路提供两个虚拟信道。 存在N / 2对相对的单向交叉链路，每对交叉链路在环结构中耦合两个完全相反的路由器。 处理电路分布在N个路由器和N个网络接口中，用于确定要在环形结构中从源元件到目的地元件的路径上发送的数据包的方向，并且用于在路径中的每个路由器处确定哪个虚拟 通道用于避免传输中的死锁。

公开(公告)号：US07554381B2

公开(公告)日：2009-06-30

申请号：US11818903

申请日：2007-06-15

Applicant: Didier Belot ,  Francesco Svelto ,  Marco Sosio ,  Massimo Brandolini

Inventor： Didier Belot ,  Francesco Svelto ,  Marco Sosio ,  Massimo Brandolini

IPC: G06F7/44

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/1491

Abstract: The mixer amplifier includes an amplification stage having a current source circuit and a plug filter adapted to modify the current circulating in the current source circuit. The amplification stage and a mixer stage amplify an incoming signal and transpose the frequency of the signal to a predetermined frequency. Resistors pairs measure the imbalance between two branches and have a relatively high value (thus creating a high-pass filter). When the branches are perfectly balanced, the voltage tapped by the non-inverting terminal of the operational amplifier A is zero. During an imbalance, this voltage rises. The output of the amplifier drives the TNP transistor T9, causing current to flow into branches to solicit the transistors T7 or T8 of the current source circuits and thus return the two branches to balance. Accordingly, a balance is maintained between the two branches by providing a feedback within the mixer amplifier.

Abstract translation: 混频器放大器包括具有电流源电路和适于修改在电流源电路中循环的电流的插头滤波器的放大级。 放大级和混频器级放大输入信号并将信号的频率转换到预定频率。 电阻对测量两个分支之间的不平衡，并具有相对较高的值（从而创建高通滤波器）。 当分支完全平衡时，运算放大器A的同相端子抽头的电压为零。 在不平衡状态下，电压上升。 放大器的输出驱动TNP晶体管T9，导致电流流入分支以吸引电流源电路的晶体管T7或T8，从而使两个分支返回平衡。 因此，通过在混频放大器内提供反馈来在两个分支之间保持平衡。