公开(公告)号：US20030090936A1

公开(公告)日：2003-05-15

申请号：US10277183

申请日：2002-10-21

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G11C016/04

CPC classification number: G11C16/20

Abstract: An electrically erasable and programmable memory (EEPROM) includes a memory array containing memory cells connected to word lines arranged in rows and to bit lines arranged in columns. The memory array includes a first special zone for storing special bits of a first type, and a second special zone for storing special bits of a second type. The first special zone includes a first row of memory cells connected to a first word line, wherein N1 memory cells are connected to N1 bit lines of a determined column of the memory array. The second special zone includes a second row of memory cells connected to a second word line, wherein N2 memory cells are connected to N2 other bit lines of the determined column. The N1 bit lines are not connected to the second row of memory cells, and the N2 bit lines are not connected to the first row of memory cells.

Abstract translation: 电可擦除可编程存储器（EEPROM）包括存储器阵列，存储器阵列包含连接到排列成行的字线和以列排列的位线的存储器单元。 存储器阵列包括用于存储第一类型的特殊位的第一特殊区域和用于存储第二类型的特殊位的第二特殊区域。 第一特殊区域包括连接到第一字线的第一行存储器单元，其中N1个存储器单元连接到存储器阵列的确定列的N1位线。 第二特殊区域包括连接到第二字线的第二行存储单元，其中N2个存储单元连接到所确定列的N2个其它位线。 N1位线未连接到第二行存储单元，N2位线未连接到第一行存储单元。

公开(公告)号：US20030071687A1

公开(公告)日：2003-04-17

申请号：US10245842

申请日：2002-09-17

Applicant: STMicroelectronics S.A.

Inventor： Marius Reffay ,  Michel Barou

IPC: H03F003/18

CPC classification number: H03F1/308 ,  H03F1/3217

Abstract: A class AB amplifier circuit includes a complementary output stage and a biasing circuit for biasing the output stage. The complementary output stage includes a P-type MOS transistor and an N-type MOS transistor, and the biasing circuit includes a bipolar transistor. The emitter and collector of the bipolar transistor are respectively connected to the gates of the P-type and N-type MOS transistors. The bipolar transistor is biased for controlling a bias voltage between the respective gates of the P-type and N-type MOS transistors.

Abstract translation: AB类放大器电路包括互补输出级和用于偏置输出级的偏置电路。 互补输出级包括P型MOS晶体管和N型MOS晶体管，偏置电路包括双极晶体管。 双极晶体管的发射极和集电极分别连接到P型和N型MOS晶体管的栅极。 双极晶体管被偏置用于控制P型和N型MOS晶体管的各个栅极之间的偏置电压。

公开(公告)号：US20030063498A1

公开(公告)日：2003-04-03

申请号：US10228164

申请日：2002-08-26

Applicant: STMICROELECTRONICS S.A.

Inventor： Cyrille Dray ,  Daniel Caspar ,  Richard Fournel

IPC: G11C007/00

CPC classification number: H01L29/42324 ,  H01L29/7887

Abstract: The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Abstract translation: FAMOS存储器位置包括根据至少两个不对称重叠轮廓（PF1，PF2）与半导体衬底的有源表面重叠的单个浮动栅极（GR），以便在有源区域中限定至少两个电极。 存储器位置编程装置（MC，SW）能够选择性地向电极施加不同的预定偏置电压组，以便在存储器位置上赋予至少三个编程逻辑电平。

公开(公告)号：US20030035329A1

公开(公告)日：2003-02-20

申请号：US10178796

申请日：2002-06-24

Applicant: STMicroelectronics S.A.

Inventor： Francois Tailliet ,  Francesco La Rosa

IPC: G11C029/00

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/08

Abstract: An electrically programmable and erasable memory includes memory cells, with each memory cell including a floating gate transistor and an access transistor. The floating gate transistor has a first terminal connected to the access transistor. The memory includes circuitry for respectively applying during an erasing phase a first signal, and a second signal on the control gate and on a second terminal of the floating gate transistors of the memory cells to be erased. The circuitry also applies to the gates of the corresponding access transistors of the memory cells to be erased a signal having a voltage that is different from a voltage of the first signal and has a low or zero potential difference with respect to a voltage of the second signal. The memory is protected against the effects from a breakdown of the gate oxide of an access transistor.

Abstract translation: 电可编程和可擦除存储器包括存储单元，其中每个存储单元包括浮栅晶体管和存取晶体管。 浮栅晶体管具有连接到存取晶体管的第一端。 存储器包括用于在擦除阶段期间分别施加第一信号的电路和在要擦除的存储器单元的控制栅极和浮置栅极晶体管的第二端子上的第二信号。 该电路还适用于存储器单元的相应存取晶体管的栅极，以被擦除具有与第一信号的电压不同的电压的信号，并且相对于第二个电压的电压具有低或零电位差 信号。 保护存储器不受存取晶体管栅极氧化物击穿的影响。

公开(公告)号：US20030016764A1

公开(公告)日：2003-01-23

申请号：US10184035

申请日：2002-06-26

Applicant: STMicroelectronics S.A.

Inventor： Jean-Marc Brossier ,  Thierry Lenez

IPC: H04L027/06 ,  H03D001/00 ,  H03H007/40

CPC classification number: H04L7/0054 ,  H04L7/0029

Abstract: A receiver for a digital data transmission device for receiving a digital signal and comprising a free sampler physically taking samples rk of a received signal r(t) at a frequency at least equal to twice the received signal spectrum maximum frequency. A digital interpolator allows to derive a sequence of samples Xk calculated from said physical samples, according to a tuning parameter null. An equalizer adjustable to a set of equalization parameters e allows to process said interpolator output samples Xk. A computing unit simultaneously provides, in a single processing, values of null to the digital interpolator and values of the equalization parameters e to the digital equalizer. The invention also provides a method for digitally processing a received signal in a digital transmission device.

Abstract translation: 一种用于数字数据传输设备的接收器，用于接收数字信号并且包括以至少等于接收信号频谱最大频率的两倍的频率物理地采集接收信号r（t）的采样rk的自由采样器。 数字插值器允许根据调谐参数tau导出从所述物理样本计算的样本序列X k。 可调整到一组均衡参数e的均衡器允许处理所述插值器输出样本Xk。 计算单元在单个处理中同时提供对数字内插器的τ值和均衡参数e到数字均衡器的值。 本发明还提供了一种在数字传输设备中数字处理接收信号的方法。

公开(公告)号：US20030011372A1

公开(公告)日：2003-01-16

申请号：US10174526

申请日：2002-06-18

Applicant: STMicroelectronics S.A.

Inventor： Jerome Nebon ,  Louis Tallaron

IPC: G01N027/416

CPC classification number: G01R22/00 ,  G01R31/3613 ,  H03F2200/261

Abstract: The amount of charge passing through a measurement resistor connected to a rechargeable battery is measured by integrating in an analog manner an overall current. This overall current is equal to the sum of the resistor current and of a reference current that selectively takes one of two opposite values. The results of the integration are compared with a reference voltage, and one of two opposite values of the reference current is selected depending on each result of the comparison. The number of times where the positive opposite value of the reference current is selected furnishes an indication on the amount of charge during the integration time.

Abstract translation: 通过连接到可再充电电池的测量电阻器的电荷量通过以模拟方式集成整体电流来测量。 该总电流等于电阻器电流和选择性地采用两个相反值之一的参考电流的总和。 将积分的结果与参考电压进行比较，并且根据比较的每个结果来选择参考电流的两个相反值中的一个。 选择参考电流的正相反值的次数提供了在积分时间期间的充电量的指示。

公开(公告)号：US20030002864A1

公开(公告)日：2003-01-02

申请号：US10172356

申请日：2002-06-14

Applicant: STMicroelectronics S.A.

Inventor： Gilles Mollie ,  Vincent de Schuyteneer

IPC: H04N005/781

CPC classification number: H04N5/76 ,  G11B20/1217 ,  H04N5/781 ,  H04N9/8042

Abstract: Several audio/video streams are recorded in an interleaved manner on logical tracks of variable sizes. These audio/video streams are selected on the basis of an allocation table contained in a random access memory, and which describes the state of occupancy of the logical tracks. The logical tracks include elementary storage portions formed of integer numbers of sectors of the disk. A chaining of the various portions is performed during recording using the index numbers of the preceding and succeeding portions, as well as indications of unknown relationships which will be updated subsequently.

Abstract translation: 在可变尺寸的逻辑磁道上以交错的方式记录多个音频/视频流。 这些音频/视频流是基于包含在随机存取存储器中的分配表来选择的，并且描述了逻辑磁道的占用状态。 逻辑磁道包括由磁盘的整数个扇区形成的基本存储部分。 在使用前后部分的索引号码的记录期间执行各部分的链接，以及将随后更新的未知关系的指示。

公开(公告)号：US20030001279A1

公开(公告)日：2003-01-02

申请号：US10184027

申请日：2002-06-27

Applicant: STMicroelectronics S.A.

Inventor： Daniel Gloria ,  Andre Perrotin

IPC: H01L023/48

CPC classification number: H01L23/66 ,  H01L23/5283 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilayer semiconductor device includes at least one structure for transmitting electrical signals, and in particular, microwave signals. The device includes at least one electrically conductive enclosure that includes a bottom plate and a top plate in two different layers. Lateral walls connect the bottom and top plates. Electrically conductive connecting strips extend into the enclosure and are in an intermediate layer, and are electrically insulated from the enclosure. The enclosure has at least one passage through which extends electrical connections of the connecting strips, which are also electrically insulated from the enclosure.

Abstract translation: 多层半导体器件包括用于传输电信号，特别是微波信号的至少一种结构。 该装置包括至少一个导电外壳，其包括底板和两个不同层中的顶板。 侧壁连接底板和顶板。 导电连接条延伸到外壳中并处于中间层，并与外壳电绝缘。 外壳具有至少一个通道，通过该通道延伸连接条的电连接，其也与外壳电绝缘。

公开(公告)号：US20020187435A1

公开(公告)日：2002-12-12

申请号：US10114428

申请日：2002-04-02

Applicant: STMICROELECTRONICS S.A.

Inventor： Serdar Manakli ,  Yorick Trouillet

IPC: G03F007/20

CPC classification number: G03F7/70466

Abstract: A method of illuminating a layer of a material, in particular a photosensitive resin, using a light source, in order to expose an area of that material to a useful dose of light for subsequent etching of that material in that area, consisting in effecting a first exposure through a pattern of a first mask made up of a central hole and peripheral holes with a first dose of light less than said useful dose, and a second exposure through a pattern of a second mask made up of a single hole with a second dose of light such that the cumulative total of said first dose induced through the central hole of the first mask and the second dose induced through the single hole of said second mask produces at least said useful dose over said area.

Abstract translation: 使用光源照射材料层，特别是感光树脂的方法，以便将该材料的区域暴露于有用剂量的光，以便随后蚀刻该区域中的该材料，该方法包括： 通过由中心孔和外围孔构成的第一掩模的图案，其具有小于所述有用剂量的第一剂量的光的第一次曝光，以及通过由单个孔构成的第二掩模的图案的第二次曝光与第二次 使得通过第一掩模的中心孔诱导的所述第一剂量的累积总和通过所述第二掩模的单个孔诱导的第二剂量在所述区域上产生至少所述有用剂量。

公开(公告)号：US20020180546A1

公开(公告)日：2002-12-05

申请号：US10126494

申请日：2002-04-19

Applicant: STMicroelectronics S.A.

Inventor： Vincent Onde

IPC: H03K007/08

CPC classification number: G06F1/025 ,  H02M7/53873 ,  H03K7/08

Abstract: A pulse-width-modulated signal is generated out of a sampled reference signal. The least significant bits of a sample of the reference signal are stored in a comparison register. At the same time, a check is made in a test circuit to find out if the sample considered corresponds to a maximum amplitude of the reference signal. If this is the case, an overflow bit is given. The overflow bit and the least significant bits of the sample considered are then linked together to obtain a comparison word. The comparison word is compared with a number given by the counter to generate the pulse-width-modulated signal.

Abstract translation: 从采样的参考信号中产生脉宽调制信号。 参考信号的采样的最低有效位被存储在比较寄存器中。 同时，在测试电路中进行检查，以确定所考虑的样本是否对应于参考信号的最大幅度。 如果是这种情况，则给出溢出位。 然后将考虑的样本的溢出位和最低有效位链接在一起以获得比较字。 将比较字与由计数器给出的数字进行比较，以产生脉宽调制信号。