公开(公告)号：US5493572A

公开(公告)日：1996-02-20

申请号：US869851

申请日：1992-04-16

Applicant: Ryoichi Hori ,  Kiyoo Itoh ,  Hitoshi Tanaka

Inventor： Ryoichi Hori ,  Kiyoo Itoh ,  Hitoshi Tanaka

IPC: G01R31/30 ,  G05F1/46 ,  G11C5/14 ,  H01L27/02 ,  G01R31/317

CPC classification number: G05F1/465 ,  G01R31/30 ,  G11C5/145 ,  G11C5/147 ,  H01L27/0218

Abstract: In a voltage converter which is disposed in a semiconductor integrated circuit so as to lower an external supply voltage and to feed the lowered voltage to a partial circuit of the integrated circuit; the voltage converter is constructed so as to produce an output voltage suited to an ordinary operation in the ordinary operation state of the semiconductor integrated circuit and an aging voltage in the aging test of the circuit.

Abstract translation: 在电压转换器中，该电压转换器设置在半导体集成电路中以降低外部电源电压并将降低的电压馈送到集成电路的部分电路; 电压转换器被构造成在半导体集成电路的普通操作状态下产生适合于普通操作的输出电压和电路的老化测试中的老化电压。

公开(公告)号：US5488513A

公开(公告)日：1996-01-30

申请号：US106574

申请日：1993-08-16

Applicant: Hitoshi Tanaka

Inventor： Hitoshi Tanaka

IPC: G02B7/04 ,  G02B7/10 ,  G03B7/00

CPC classification number: G02B7/10

Abstract: A zoom lens barrel is provided including a cam ring which is threadedly engaged to a female helicoid formed in a stationary barrel, a linear movement guide member that is rotatable relative to the cam ring and movable in an optical axis direction together with the cam ring, and movable lens groups, including first, second and third lens groups that are guided in the optical axis direction by the linear movement guide member. The zoom lens barrel further includes a female helicoid formed on an inner peripheral surface of the cam ring to engage with a male helicoid of a first lens frame which holds the first lens group and a plurality of cam grooves formed on the cam ring to drive lens groups behind the first lens group.

Abstract translation: 一种变焦透镜镜筒，包括：凸轮环，该凸轮环螺纹地接合到形成在固定镜筒中的阴螺纹;线性移动引导构件，其可相对于所述凸轮环旋转并与所述凸轮环一起沿光轴方向移动; 以及可移动透镜组，包括通过线性移动引导构件在光轴方向上被引导的第一，第二和第三透镜组。 变焦透镜筒还包括形成在凸轮环的内周表面上的阴螺纹，以与固定第一透镜组的第一透镜框架的阳螺旋形状和形​​成在凸轮环上的多个凸轮槽接合以驱动透镜 第一透镜组后面的组。

公开(公告)号：US5402375A

公开(公告)日：1995-03-28

申请号：US207679

申请日：1994-03-09

Applicant: Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

Inventor： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

IPC: G05F1/46 ,  H03K17/693 ,  G11C7/00

CPC classification number: H03K17/693 ,  G05F1/465

Abstract: In a voltage converter provided in a semiconductor memory and supplying an internal supply voltage to a circuit in the semiconductor memory, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as voltage dividing means. The memory also includes a word line booster for boosting the internal supply voltage.

Abstract translation: 在设置在半导体存储器中的电压转换器中并向半导体存储器中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路 被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。 电压转换器包括彼此互连的MOS晶体管和差分放大器，以及分压装置。 该存储器还包括用于升高内部电源电压的字线升压器。

公开(公告)号：US5376839A

公开(公告)日：1994-12-27

申请号：US104340

申请日：1993-08-09

Applicant: Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

Inventor： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

IPC: G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/02 ,  H03K3/01 ,  H03K3/26

CPC classification number: G05F1/465 ,  G05F3/245 ,  G05F3/247 ,  G11C11/4074 ,  G11C5/147 ,  H01L27/0203

Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

Abstract translation: 涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。 可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。 提供了改进的测试这些电路的方法。

公开(公告)号：US5316727A

公开(公告)日：1994-05-31

申请号：US936079

申请日：1992-08-28

Applicant: Yoshiro Suzuki ,  Hitoshi Tanaka ,  Noriyuki Kurihara ,  Yutaka Saito

Inventor： Yoshiro Suzuki ,  Hitoshi Tanaka ,  Noriyuki Kurihara ,  Yutaka Saito

IPC: G01N21/01 ,  G01N21/27 ,  G01N21/78 ,  G01N21/86

CPC classification number: G01N21/8483 ,  G01N21/272 ,  G01N2021/478 ,  G01N21/78 ,  G01N2201/0256 ,  G01N2201/1241 ,  G01N2201/126

Abstract: A measuring apparatus of the present invention measures the constituent concentration of a specimen after loading into the apparatus a test piece having a test material which develops coloring as a result of a reaction with the constituents of a specimen. When the apparatus detects that the test piece having the test material has been loaded, it automatically begins to measure the constituent concentration of the specimen. That is, after the loading of the test piece is detected, a predetermined time period is measured. During this time measurement, the time period is displayed at a predetermined time interval. After the time measurement of this predetermined time period is terminated, the test material is irradiated with a light, and the intensity of the light from the test material is detected. The constituent concentration of the specimen applied to the test material can be determined on the basis of the reflected light intensity thus detected. Furthermore, this measuring apparatus can detect a reverse insertion of a test piece, and is constructed so as to disable the measurement of the constituent concentration of a specimen if supplementary information to be stored along with measurement information has not been set.

Abstract translation: 本发明的测量装置测量在装入装置之后的样品的成分浓度，该试片具有由于与试样的组分的反应而产生着色的试验材料。 当设备检测到具有测试材料的测试件已经被加载时，其自动开始测量样品的组分浓度。 也就是说，在检测到试件的加载之后，测量预定时间段。 在该时间测量期间，以预定的时间间隔显示时间段。 在该预定时间段的时间测量结束之后，用光照射测试材料，并且检测来自测试材料的光的强度。 可以基于这样检测的反射光强度来确定施加到测试材料上的试样的组分浓度。 此外，该测量装置可以检测试件的反向插入，并且构造成如果尚未设置要与存储的补充信息一起设置的样本的成分浓度的测量，则不能进行测量。

公开(公告)号：US5305145A

公开(公告)日：1994-04-19

申请号：US907807

申请日：1992-07-02

Applicant: Hitoshi Tanaka

Inventor： Hitoshi Tanaka

IPC: G02B7/02 ,  G02B23/22 ,  G03B17/08

CPC classification number: G02B23/22 ,  G02B7/02 ,  G03B17/08

Abstract: A waterproof lens including a lens frame located within a lens barrel. An inner peripheral flange is provided on the inner periphery of the lens barrel. The waterproof lens also has a tubular member which is detachably mounted to the inner peripheral flange for the purpose of intercepting light in a space between the lens barrel and the lens frame. An elastic waterproof ring is provided on the outer peripheral surface of the tubular member. The waterproof lens further includes a mechanism for sealing the transparent member and the inner peripheral flange in a water-tight manner.

Abstract translation: 一种防水透镜，包括位于镜筒内的透镜框。 在镜筒的内周设有内周缘。 防水透镜还具有可拆卸地安装到内周边缘的管状构件，用于遮挡镜筒和透镜框之间的空间中的光。 在管状部件的外周面上设有弹性防水环。 防水透镜还包括用于以不透水的方式密封透明构件和内周边凸缘的机构。

公开(公告)号：US5301142A

公开(公告)日：1994-04-05

申请号：US895598

申请日：1992-06-08

Applicant: Yukihide Suzuki ,  Masaya Muranaka ,  Hiromi Matsuura ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Eiji Yamasaki ,  Toshiyuki Sakuta

Inventor： Yukihide Suzuki ,  Masaya Muranaka ,  Hiromi Matsuura ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Eiji Yamasaki ,  Toshiyuki Sakuta

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C29/00 ,  G11C29/34 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC classification number: G11C7/10

Abstract: Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend. These include a first main amplifier comprising a static current mirror amplifier which requires a relatively large operating current and a second main amplifier comprising a dynamic CMOS latch amplifier which requires only a relatively small operating current. These main amplifiers are put to proper use in conformity with the operating mode involved. By virtue of these arrangements, the number of parallel bits in a multibit parallel test mode of a dynamic RAM becomes expandable without being restricted by the number of the sub-IO lines correspondingly provided for each memory mat.

Abstract translation: 在字线和位线延伸的方向上，多个存储器阵列中的每一个被分成多个存储器块MAT00L-MAT07L到MAT10R-MAT17R。 提供了与这些存储垫对应并且与字线平行设置的第一公共数据线，即子IO线。 指定对应的存储器垫的位线选择性地连接到第一公共数据线。 还提供第二公共数据线，即主IO线组MIOG0-MIOG7，并且与位线并行设置。 指定的子IO线选择性地连接到第二公共数据线。 此外，形成主放大器单元MAU0的多个主放大器在位线延伸的方向上有序排列。 这些包括第一主放大器，其包括需要相对大的工作电流的静态电流镜放大器，以及包括仅需要较小工作电流的动态CMOS锁存放大器的第二主放大器。 这些主放大器按照所涉及的工作模式正确使用。 由于这些布置，动态RAM的多位并行测试模式中的并行比特数可以扩展，而不受对应于每个存储器垫的子IO线数的限制。

公开(公告)号：US5262993A

公开(公告)日：1993-11-16

申请号：US789024

申请日：1991-11-06

Applicant: Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

Inventor： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

IPC: G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C29/83 ,  G11C29/832 ,  G11C5/14

Abstract: In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.

Abstract translation: 在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。 另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。 开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。 然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

公开(公告)号：US5254880A

公开(公告)日：1993-10-19

申请号：US863705

申请日：1992-04-03

Applicant: Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin ichi Ikenaga

Inventor： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin ichi Ikenaga

IPC: G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/02 ,  H03K3/01 ,  H03K5/01

CPC classification number: G05F1/465 ,  G05F3/245 ,  G05F3/247 ,  G11C11/4074 ,  G11C5/147 ,  H01L27/0203

Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

Abstract translation: 涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。 可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。 提供了改进的测试这些电路的方法。

公开(公告)号：US5247054A

公开(公告)日：1993-09-21

申请号：US561643

申请日：1990-08-01

Applicant: Hitoshi Tanaka ,  Tsuneyuki Sato ,  Todatoshi Ota, deceased ,  Michio Sasaoka

Inventor： Hitoshi Tanaka ,  Tsuneyuki Sato ,  Todatoshi Ota, deceased ,  Michio Sasaoka

IPC: C08F2/58 ,  C08F2/00 ,  C08G61/00 ,  H01F1/42

CPC classification number: H01F1/42 ,  C08G61/00

Abstract: An organic polymer ferromagnetic material characterized in that the material comprises a polymer obtained by subjecting to plasma polymerization or oxidation polymerization a methane derivative having two substituents and represented by the formula ##STR1## wherein A is an electron accepting group, and B is an electron donating group, or by copolymerizing the methane derivative with a diarylmethane derivative represented by the formula ##STR2## wherein R.sup.1 is a substituted or unsubstituted phenyl group by plasma polymerization or oxidation polymerization.