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    Semiconductor memory
    1.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5301142A

    公开(公告)日：1994-04-05

    申请号：US895598

    申请日：1992-06-08

    申请人： Yukihide Suzuki ,  Masaya Muranaka ,  Hiromi Matsuura ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Eiji Yamasaki ,  Toshiyuki Sakuta

    发明人： Yukihide Suzuki ,  Masaya Muranaka ,  Hiromi Matsuura ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Eiji Yamasaki ,  Toshiyuki Sakuta

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C29/00 ,  G11C29/34 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

    CPC分类号： G11C7/10

    摘要： Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend. These include a first main amplifier comprising a static current mirror amplifier which requires a relatively large operating current and a second main amplifier comprising a dynamic CMOS latch amplifier which requires only a relatively small operating current. These main amplifiers are put to proper use in conformity with the operating mode involved. By virtue of these arrangements, the number of parallel bits in a multibit parallel test mode of a dynamic RAM becomes expandable without being restricted by the number of the sub-IO lines correspondingly provided for each memory mat.

    摘要翻译： 在字线和位线延伸的方向上，多个存储器阵列中的每一个被分成多个存储器块MAT00L-MAT07L到MAT10R-MAT17R。 提供了与这些存储垫对应并且与字线平行设置的第一公共数据线，即子IO线。 指定对应的存储器垫的位线选择性地连接到第一公共数据线。 还提供第二公共数据线，即主IO线组MIOG0-MIOG7，并且与位线并行设置。 指定的子IO线选择性地连接到第二公共数据线。 此外，形成主放大器单元MAU0的多个主放大器在位线延伸的方向上有序排列。 这些包括第一主放大器，其包括需要相对大的工作电流的静态电流镜放大器，以及包括仅需要较小工作电流的动态CMOS锁存放大器的第二主放大器。 这些主放大器按照所涉及的工作模式正确使用。 由于这些布置，动态RAM的多位并行测试模式中的并行比特数可以扩展，而不受对应于每个存储器垫的子IO线数的限制。

    Semiconductor memory operating with low supply voltage
    2.
    发明授权
    Semiconductor memory operating with low supply voltage 失效
    半导体存储器以低电源电压工作

    公开(公告)号：US5264743A

    公开(公告)日：1993-11-23

    申请号：US621064

    申请日：1990-11-29

    申请人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Hitoshi Tanaka ,  Yasushi Watanabe ,  Eiji Kume ,  Masanori Isoda ,  Eiji Yamasaki ,  Tatsumi Uchigiri

    发明人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Hitoshi Tanaka ,  Yasushi Watanabe ,  Eiji Kume ,  Masanori Isoda ,  Eiji Yamasaki ,  Tatsumi Uchigiri

    IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C8/08 ,  H03K19/00

    CPC分类号： G11C7/1069 ,  G11C5/147 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1051 ,  G11C8/08

    摘要： The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.

    摘要翻译： 本发明旨在以低电压高速运行半导体器件。 使用电路配置，其中根据是要读取还是写入信息，在公共I / O线和数据线之间的传输阻抗改变。 提供了一种电流/电压转换器，其包括与选择的MISFET不同的导电类型的MISFET。 因此，读取信息的速度增加。 提供具有高驱动能力的中间电压发生器。 因此，对具有大负载电容的LSI具有足够的驱动能力。 提供了一种电压转换器，其将数据线电源电压或字线电源电压转换为更高的电压。 因此，确保了稳定的信号传输。

    Semiconductor memory operating with low supply voltage
    3.
    发明授权
    Semiconductor memory operating with low supply voltage 失效
    半导体存储器以低电源电压工作

    公开(公告)号：US5555215A

    公开(公告)日：1996-09-10

    申请号：US539724

    申请日：1995-10-05

    申请人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Hitoshi Tanaka ,  Yasushi Watanabe ,  Eiji Kume ,  Masanori Isoda ,  Eiji Yamasaki ,  Tatsumi Uchigiri

    发明人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Hitoshi Tanaka ,  Yasushi Watanabe ,  Eiji Kume ,  Masanori Isoda ,  Eiji Yamasaki ,  Tatsumi Uchigiri

    IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C8/08 ,  G11C11/401

    CPC分类号： G11C7/1069 ,  G11C5/147 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1051 ,  G11C8/08

    摘要： The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.

    摘要翻译： 本发明旨在以低电压高速运行半导体器件。 使用电路配置，其中根据是要读取还是写入信息，在公共I / O线和数据线之间的传输阻抗改变。 提供了一种电流/电压转换器，其包括与选择的MISFET不同的导电类型的MISFET。 因此，读取信息的速度增加。 提供具有高驱动能力的中间电压发生器。 因此，对具有大负载电容的LSI具有足够的驱动能力。 提供了一种电压转换器，其将数据线电源电压或字线电源电压转换为更高的电压。 因此，确保了稳定的信号传输。

    High-speed semicondustor memory integrated circuit arrangement having power and signal lines with reduced resistance
    4.
    发明授权
    High-speed semicondustor memory integrated circuit arrangement having power and signal lines with reduced resistance 失效
    高速半导体存储器集成电路布置具有功率和信号线，电阻降低

    公开(公告)号：US5280450A

    公开(公告)日：1994-01-18

    申请号：US695983

    申请日：1991-05-06

    申请人： Yoshinobu Nakagome ,  Eiji Kume ,  Kiyoo Itoh ,  Hitoshi Tanaka

    发明人： Yoshinobu Nakagome ,  Eiji Kume ,  Kiyoo Itoh ,  Hitoshi Tanaka

    IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/10 ,  G11C11/40

    CPC分类号： G11C7/065 ,  G11C5/14 ,  G11C7/10 ,  G11C7/1006

    摘要： A semiconductor integrated circuit is disclosed, in which a group of sense amplifiers activated at the same time by a selection signal on a selection signal line are divided into a plurality of blocks, and a power-source line for driving sense amplifiers is formed for each sense amplifier block so as to cross the selection signal line. Alternatively, an input/output line is divided into a plurality of sub-input/output lines, and a plurality of input/output lines are formed so that each input/output line crosses its sub-input/output lines, to form a hierarchical structure with respect to input/output lines. Thus, the load capacitance of each power-source line is reduced, and the time constant of each of the charging and discharging of the load capacitance is decreased. That is, the above semiconductor integrated circuit can operate at high speed.

    摘要翻译： 公开了一种半导体集成电路，其中通过选择信号线上的选择信号同时激活的一组读出放大器被分成多个块，并且为每个块形成用于驱动读出放大器的电源线 读出放大器块，以便跨越选择信号线。 或者，输入/输出线被分成多个子输入/输出线，并且形成多个输入/输出线，使得每个输入/输出线与其子输入/输出线交叉，以形成分级 相对于输入/输出线的结构。 因此，每个电源线的负载电容减小，并且负载电容的充电和放电的每个的时间常数减小。 也就是说，上述半导体集成电路可以高速运行。

    Voltage converter of semiconductor device
    5.
    发明授权
    Voltage converter of semiconductor device 失效
    半导体器件的电压转换器

    公开(公告)号：US5272393A

    公开(公告)日：1993-12-21

    申请号：US790065

    申请日：1991-11-12

    申请人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

    发明人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

    IPC分类号： G05F1/46 ,  H03K17/693 ,  H03K3/01 ,  H03K5/22

    CPC分类号： H03K17/693 ,  G05F1/465

    摘要： In a voltage converter provided in a semiconductor device and supplying an internal supply voltage to a circuit in the semiconductor device, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. Another circuit selects the first voltage when the semiconductor device is in a state of a standard operation and selects the second voltage when the device is in another state of operation, such as testing or aging. The selected voltage may be converted by a differential amplifier which is constituted by a load of P-channel MOS transistors and a source-coupled pair of N-channel MOS transistors. An output of the differential amplifier is fed back through a directly coupled voltage lowering circuit which generates the converted output.

    摘要翻译： 在设置在半导体器件中的电压转换器中并向半导体器件中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路 被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。 当半导体器件处于标准操作状态时，另一个电路选择第一电压，并且当器件处于另一种操作状态（例如测试或老化）时选择第二电压。 所选择的电压可以由由P沟道MOS晶体管的负载和源极耦合的N沟道MOS晶体管对构成的差分放大器来转换。 差分放大器的输出通过直接耦合的降压电路反馈，该电路产生转换的输出。

    Large scale integrated circuit for low voltage operation
    6.
    发明授权
    Large scale integrated circuit for low voltage operation 失效
    用于低压运行的大规模集成电路

    公开(公告)号：US5262999A

    公开(公告)日：1993-11-16

    申请号：US838505

    申请日：1992-03-24

    申请人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    发明人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096 ,  G11C7/00

    CPC分类号： G11C5/147 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096

    摘要： Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

    摘要翻译： 公开了一种单芯片ULSI，其可以在宽范围的电源电压（1V至5.5V）中进行固定操作。 该单芯片ULSI由一个电压转换器电路组成，该电路用于宽范围电源电压的固定内部电压，可适用于多个输入/输出电平的输入/输出缓冲器，一个动态RAM 可以在2V以下的电源电压下工作的这种单芯片ULSI可以应用于紧凑型便携式电子设备，例如笔记本型个人计算机，电子口袋笔记本， 固态摄像机等