公开(公告)号：US10198219B2

公开(公告)日：2019-02-05

申请号：US15608370

申请日：2017-05-30

Applicant: ATI Technologies ULC

Inventor： Gabor Sines

IPC: G06F3/06 ,  G06F9/48 ,  G06F9/50 ,  G06F17/28 ,  G06F17/30

Abstract: Described herein is a method and apparatus for en route translation of data by a data translation logic (DTL) on a solid state graphics (SSG) device as the data moves from a first memory architecture on the SSG device to a second memory architecture associated with a graphics processing units (GPU) on the SSG device or from the first memory architecture on the SSG device to a host memory in a host system that is connected to the SSG device.

公开(公告)号：US20190028725A1

公开(公告)日：2019-01-24

申请号：US16126704

申请日：2018-09-10

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lei Zhang ,  Ji Zhou ,  Zhen Chen ,  Min Yu

IPC: H04N19/423 ,  H04N19/33 ,  H04N19/159 ,  H04N19/117 ,  H04N19/187 ,  H04N19/59 ,  H04N19/80

Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.

公开(公告)号：US20190018699A1

公开(公告)日：2019-01-17

申请号：US15663499

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Asaro ,  Yinan Jiang ,  Andy Sung ,  Ahmed M. Abdelkhalek ,  Xiaowei Wang ,  Sidney D. Fortes

IPC: G06F9/455 ,  G06F9/48

Abstract: A technique for recovering from a hang in a virtualized accelerated processing device (“APD”) is provided. In the virtualization scheme, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD stops operations for a current VM and starts operations for another VM. To stop operations on the APD, a virtualization scheduler sends a request to idle the APD. The APD responds by completing work and idling. If one or more portions of the APD do not complete this idling process before a timeout expires, then a hang occurs. In response to the hang, the virtualization scheduler informs the hypervisor that a hang has occurred. The hypervisor performs a function level reset on the APD and informs the VM that the hang has occurred. The VM responds by stopping command issue to the APD and re-initializing the APD for the function.

公开(公告)号：US10176548B2

公开(公告)日：2019-01-08

申请号：US14974585

申请日：2015-12-18

Applicant: ATI TECHNOLOGIES ULC

Inventor： Gongxian Jeffrey Cheng

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G09G5/393 ,  G09G5/395

Abstract: A processor includes a scheduler that governs which of a plurality of pending graphics contexts is selected for execution at a graphics pipeline of the processor. The processor also includes a plurality of flip queues storing data ready to be rendered at a display device. The executing graphics context can issue a flip request to change data at stored at one of the flip queues. In response to determining that the flip request targets a flip queue that is being used for rendering at the display device, the scheduler executes a context switch to schedule a different graphics context for execution at the graphics pipeline.

公开(公告)号：US10169843B1

公开(公告)日：2019-01-01

申请号：US15818072

申请日：2017-11-20

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Ihab Amer ,  Guennadi Riguer ,  Ruijin Wu ,  Skyler J. Saleh ,  Boris Ivanovic ,  Gabor Sines

IPC: G06T3/40 ,  G06T7/136 ,  G06T7/13 ,  G06T7/246

Abstract: A processing system selectively renders pixels or blocks of pixels of an image and leaves some pixels or blocks of pixels unrendered to conserve resources. The processing system generates a motion vector field to identify regions of an image having moving areas. The processing system uses a rendering processor to identify as regions of interest those units having little to no motion, based on the motion vector field, and a large amount of edge activity, and to minimize the probability of unrendered pixels, or “holes”, in these regions. To avoid noticeable patterns, the rendering processor applies a probability map to determine the possible locations of holes, assigning to each unit a probability indicating the percentage of pixels within the unit that will be holes, and assigning a lower probability to units identified as regions of interest.

公开(公告)号：US20180349286A1

公开(公告)日：2018-12-06

申请号：US15608343

申请日：2017-05-30

Applicant: ATI Technologies ULC

Inventor： Dhirendra Partap Singh Rana

IPC: G06F12/1009 ,  G06F12/10

Abstract: Techniques for managing page tables for an accelerated processing device are provided. The page tables for the accelerated processing device include a primary page table and secondary page tables. The page size selected for any particular secondary page table is dependent on characteristics of the memory allocations for which translations are stored in the secondary page table. Any particular memory allocation is associated with a particular “initial” page size. Translations for multiple allocations may be placed into a single secondary page table, and a particular page size is chosen for all such translations. The page size is the smallest of the natural page sizes for the allocations that are not using a translate further technique. The translation further technique is a technique wherein secondary page table entries do not themselves provide translations but instead point to an additional page table level referred to as the translate further page table level.

公开(公告)号：US10097835B2

公开(公告)日：2018-10-09

申请号：US14638503

申请日：2015-03-04

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Khaled Mammou ,  Ihab M. A. Amer ,  Oleksandr O. Bobrovnik ,  Vladyslav S. Zakharchenko

IPC: H04N19/136 ,  H04N19/177 ,  H04N19/50 ,  H04N19/147 ,  H04N19/114 ,  H04N19/19

Abstract: A method of video encoding is disclosed which is content adaptive. The encoding method is automatically adjusted to optimize the encoding, the adjusting depending on the content of the pictures being encoded. A system for implementing the method and a non-transitory computer-readable storage medium for storing instructions of the method are also disclosed.

公开(公告)号：US10045003B2

公开(公告)日：2018-08-07

申请号：US15099247

申请日：2016-04-14

Applicant: ATI Technologies ULC

Inventor： Jiao Wang ,  Mohamed K. Cherif

IPC: H04N13/00 ,  H04N19/103 ,  H04N19/597 ,  H04N19/139 ,  H04N19/176 ,  H04N19/147

Abstract: A method for determining a macroblock (MB) coding mode for a current MB in a dependent view. A window around a co-located MB in a base view is determined, wherein the co-located MB is a MB in the base view having a same location as the current MB in the dependent view. A coding mode complexity value (CMCV) is determined for each MB in the window, wherein the CMCV is based on a coding mode used to encode the MB. Rate distortion optimization (RDO) is performed for the current MB using a reduced number of coding modes if a total CMCV for all MBs in the window is less than a threshold, or using all supported coding modes if the total CMCV for all MBs in the window is greater than the threshold. A coding mode for the current MB is determined based on the RDO results.

公开(公告)号：US20180217844A1

公开(公告)日：2018-08-02

申请号：US15417555

申请日：2017-01-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： John Kalamatianos ,  Greg Sadowski ,  Syed Zohaib M. Gilani

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06F12/0875

CPC classification number: G06F9/3836 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3887 ,  G06F12/0875 ,  G06F15/8007 ,  G06F2212/452

Abstract: A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available, the selected instruction is executed on the SIMD pipeline unit. The self-timed arithmetic pipeline unit (SIMD pipeline unit) is effectively encapsulated in a synchronous, (e.g., clocked by global clock), scheduler and register file environment.

公开(公告)号：US20180181520A1

公开(公告)日：2018-06-28

申请号：US15582479

申请日：2017-04-28

Applicant: ATI Technologies ULC

Inventor： Nima Osqueizadeh

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4282

Abstract: Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.