公开(公告)号：US09032354B2

公开(公告)日：2015-05-12

申请号：US13903847

申请日：2013-05-28

Applicant: STMicroelectronics, Inc.

Inventor： Razak Hossain

IPC: G06F17/50 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318575 ,  G01R31/318577

Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

公开(公告)号：US20150126003A1

公开(公告)日：2015-05-07

申请号：US14596625

申请日：2015-01-14

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu

IPC: H01L21/8238 ,  H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823821 ,  H01L21/845

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made on the bottom portion to produce a silicon-germanium region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由硅半导体材料形成的SOI衬底层包括相邻的第一和第二区域。 去除第二区域中的硅衬底层的一部分，使得第二区域保持由硅半导体材料制成的底部。 硅 - 锗半导体材料的外延生长在底部制成以产生硅 - 锗区。 图案化硅区域以限定第一（例如，n沟道）导电类型的FinFET的第一鳍结构。 硅 - 锗区域也被图案化以限定第二（例如p沟道）导电类型的FinFET的第二鳍结构。

公开(公告)号：US09024471B2

公开(公告)日：2015-05-05

申请号：US13461173

申请日：2012-05-01

Applicant: Oleg Logvinov

Inventor： Oleg Logvinov

IPC: H05B37/02 ,  H04B3/54 ,  H05B37/00

CPC classification number: H05B37/0254 ,  H04B3/54 ,  Y02B20/48 ,  Y10T307/391 ,  Y10T307/406

Abstract: In accordance with an embodiment, a method of operating a node coupled to a power network and a communications link includes receiving a status from a further node coupled to the power network via the communications link, and adjusting a power consumption of a device coupled to the node and powered by the power network based on the status message and based on a first rule set.

Abstract translation: 根据实施例，操作耦合到电力网络和通信链路的节点的方法包括经由通信链路从耦合到电力网络的另一节点接收状态，以及调整耦合到电力网络的设备的功率消耗 节点，并且基于状态消息并基于第一规则集由电力网络供电。

公开(公告)号：US09024408B2

公开(公告)日：2015-05-05

申请号：US12981383

申请日：2010-12-29

Applicant: Ming Fang

Inventor： Ming Fang

IPC: H01L27/24 ,  B41J2/16 ,  B81C1/00 ,  G01P15/00

CPC classification number: H01L27/24 ,  B41J2/1601 ,  B41J2/1607 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1635 ,  B41J2/1639 ,  B41J2/1643 ,  B81C1/00246 ,  G01P15/00

Abstract: A method of manufacturing double-sided semiconductor die by performing a first plurality of processes to a first side of a wafer and performing a second plurality of processes to a second side of the wafer, thereby forming at least a first semiconductor device on the first side of the wafer and at least a second semiconductor device on the second side of the wafer. The wafer may be cut to form a plurality of die having at least one semiconductor device on each side.

Abstract translation: 一种通过对晶片的第一面执行第一多个工艺并对晶片的第二侧执行第二多个工艺来制造双面半导体管芯的方法，从而在第一侧上形成至少第一半导体器件 以及晶片第二面上的至少第二半导体器件。 可以切割晶片以形成在每一侧具有至少一个半导体器件的多个裸片。

公开(公告)号：US20150116090A1

公开(公告)日：2015-04-30

申请号：US14508008

申请日：2014-10-07

Applicant: STMicroelectronics, Inc.

Inventor： Gregory Proehl

IPC: H04B5/00 ,  G06K7/10 ,  H01F38/14

CPC classification number: H04B5/0037 ,  G06K7/10297 ,  H01F27/362 ,  H01F38/14 ,  H04B5/0031 ,  H04B5/0075

Abstract: A near-field magnetic induction system includes a metallic structure, an amorphous metal barrier and a near-field magnetic induction device. The device includes an antenna coupled to the amorphous metal barrier and a circuit electrically coupled to the antenna. In use, the antenna is separated from the metallic structure by the amorphous metal barrier. The amorphous metal barrier may be integrated with the near-field magnetic induction device or with the metallic structure. Inductive coupling with the near-field magnetic induction device may be used, for example, in communication or energy transfer applications such as RFID tags and inductive chargers.

Abstract translation: 近场磁感应系统包括金属结构，非晶金属屏障和近场磁感应装置。 该装置包括耦合到非晶金属屏障的天线和电耦合到天线的电路。 在使用中，天线通过非晶金属屏障与金属结构分离。 非晶态金属屏障可以与近场磁感应装置或金属结构集成。 与近场磁感应装置的感应耦合可用于例如通信或能量转移应用，如RFID标签和感应充电器。

公开(公告)号：US09018051B2

公开(公告)日：2015-04-28

申请号：US14164055

申请日：2014-01-24

Applicant: STMicroelectronics, Inc.

Inventor： Barry Dove

IPC: H01L21/335 ,  H01L29/66 ,  H01L21/28 ,  H01L23/522 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L21/28114 ,  H01L23/5226 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.

Abstract translation: 提供了一种应变增强型晶体管，其具有覆盖栅电极的应变诱导层。 栅电极在晶体管的沟道区域上具有倾斜的侧壁。

公开(公告)号：US20150102496A1

公开(公告)日：2015-04-16

申请号：US14053531

申请日：2013-10-14

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal interconnections are formed in an integrated circuit by forming a wide trench in a dielectric layer. A dielectric fin of a second dielectric material is formed in the trench. Conductive plugs and metal lines are formed on both sides of the fin.

Abstract translation: 通过在电介质层中形成宽的沟槽，在集成电路中形成金属互连。 在沟槽中形成第二电介质材料的绝缘片。 导电插头和金属线形成在鳍的两侧。

公开(公告)号：US20150102412A1

公开(公告)日：2015-04-16

申请号：US14050576

申请日：2013-10-10

Applicant: STMicroelectronics, Inc.

Inventor： PIERRE MORIN ,  Qing Liu ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上半导体（SOI）晶片的第一半导体层上形成第二半导体层，该第二半导体层包括与第一半导体层的第一半导体材料不同的第二半导体材料。 该方法还可以包括在非氧化性气氛中进行热处理，以将第二半导体材料扩散到第一半导体层中，以及去除第二半导体层。

公开(公告)号：US20150093861A1

公开(公告)日：2015-04-02

申请号：US14042884

申请日：2013-10-01

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

IPC: H01L21/84

CPC classification number: H01L21/84

Abstract: An SOI substrate includes first and second active regions separated by STI structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks. An oxide layer and nitride layer are then deposited. Using a mask, the nitride layer over the first active region is removed, and the mask and oxide layer are removed to expose the SOI substrate in the first active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the first active region and a protective nitride layer is deposited. The masking, nitride layer removal, and oxide layer removal steps are then repeated to expose the SOI in the second active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the second active region.

Abstract translation: SOI衬底包括由STI结构分离并且包括栅叠层的第一和第二有源区。 在包括栅极堆叠的第一和第二区域上共形沉积的间隔层被定向蚀刻以沿着栅极堆叠的侧面限定侧壁间隔物。 然后沉积氧化物层和氮化物层。 使用掩模，去除第一有源区上的氮化物层，去除掩模和氧化物层以暴露第一有源区中的SOI衬底。 然后在第一有源区中与栅叠层相邻地外延生长凸起的源极 - 漏极结构，并且沉积保护性氮化物层。 然后重复掩模，氮化物层去除和氧化物层去除步骤以暴露第二有源区域中的SOI。 然后在第二活性区域中与栅叠层相邻地外延生长凸起的源极 - 漏极结构。

公开(公告)号：US08996967B2

公开(公告)日：2015-03-31

申请号：US12852368

申请日：2010-08-06

Applicant: Mustafa N. Kaynak ,  Alessandro Risso ,  Patrick R. Khayat

Inventor： Mustafa N. Kaynak ,  Alessandro Risso ,  Patrick R. Khayat

IPC: G06F11/00 ,  H03M13/29 ,  G11B20/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/09 ,  H03M13/19

CPC classification number: H03M13/2915 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/10175 ,  G11B20/10194 ,  G11B20/10222 ,  G11B20/10296 ,  G11B20/10379 ,  G11B20/1833 ,  G11B2020/1853 ,  G11B2020/1863 ,  G11B2220/2516 ,  H03M13/098 ,  H03M13/13 ,  H03M13/19 ,  H03M13/2918 ,  H03M13/2927 ,  H03M13/293 ,  H03M13/6343

Abstract: An embodiment of a data write path includes encoder and write circuits. The encoder circuit is configured to code data so as to render detectable a write error that occurs during a writing of the coded data to a storage medium, and the write circuit is configured to write the coded data to the storage medium. For example, such an embodiment may allow rendering detectable a write error that occurs while writing data to a bit-patterned storage medium.

Abstract translation: 数据写入路径的实施例包括编码器和写入电路。 编码器电路被配置为对数据进行编码，以便可读取在将编码数据写入存储介质期间发生的写错误，并且写电路被配置为将编码数据写入存储介质。 例如，这样的实施例可以允许可读出在将数据写入位图案存储介质时发生的写入错误。