Alteration of a signal value for an FPGA at runtime

    公开(公告)号:US10311193B2

    公开(公告)日:2019-06-04

    申请号:US14823197

    申请日:2015-08-11

    Abstract: A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.

    METHOD FOR PROVIDING A REAL-TIME-CAPABLE SIMULATION FOR CONTROL UNIT DEVELOPMENT, AND SIMULATION DEVICE FOR CONTROL UNIT DEVELOPMENT

    公开(公告)号:US20190073437A1

    公开(公告)日:2019-03-07

    申请号:US16113560

    申请日:2018-08-27

    Abstract: A method for providing a real-time-capable simulation for control unit development, wherein the real-time-capable simulation simulates a control unit or an environment of a control unit or a combination of a control unit and an environment of the control unit. The real-time-capable simulation has a co-simulation of a real-time-capable sub-simulation and a non-real-time-capable sub-simulation that interacts with the real-time-capable sub-simulation, wherein the real-time-capable sub-simulation and the non-real-time-capable sub-simulation are designed for communication of simulation data. The real-time-capable sub-simulation has a first simulation time corresponding to real time and the non-real-time-capable sub-simulation has a virtual, second simulation time that is coupled to the first simulation time and that matches the first simulation time at the start of the real-time-capable simulation.

    METHOD AND SYSTEM FOR AUTOMATIC CODE GENERATION

    公开(公告)号:US20180088911A1

    公开(公告)日:2018-03-29

    申请号:US15273992

    申请日:2016-09-23

    CPC classification number: G06F8/34 G06F8/443 G06F8/71

    Abstract: A method for generating production code from a block diagram on a host computer is provided. A block in the block diagram has a number of input ports for receiving signals and a number of output ports for sending signals. The processor identifies a first block in the block diagram. The input signal is traced back to a second block upstream of the first block. Compliance with a optimization condition is checked, the optimization condition being fulfilled when a group of adjacent blocks has an assignment operation that affects one or more elements of the input signal while leaving at least one element of the composite variable unchanged. A combined production code is generated for the group of adjacent blocks when the optimization condition is fulfilled so that the combined production code includes write instructions for those elements of the composite variable that are affected by the assignment operation.

    METHOD FOR CREATING AN FPGA NETLIST
    207.
    发明申请

    公开(公告)号:US20170329877A1

    公开(公告)日:2017-11-16

    申请号:US15585335

    申请日:2017-05-03

    CPC classification number: G06F17/505 G06F17/5027 G06F17/5054

    Abstract: A method for creating an FPGA netlist generated from an FPGA source code and at least one shadow register. The FPGA source code defines at least one function and at least one signal. The shadow register is assigned to the at least one signal, and is arranged and provided to store the value of the assigned signal at runtime. An option for reading out the stored signal value at runtime is provided. The function defined in the FPGA source code is not changed by the shadow register. The function described by the FPGA source code is executed by the FPGA, and a functional decoupling of the shadow register from the function described in the FPGA source code is provided. Via the decoupling, the shadow register maintains the signal value stored at the time of the decoupling while the function described in the FPGA source code is being executed.

    CALCULATING A DESIRED TRAJECTORY
    209.
    发明申请
    CALCULATING A DESIRED TRAJECTORY 审中-公开
    计算所需的TRAJECTORY

    公开(公告)号:US20170045418A1

    公开(公告)日:2017-02-16

    申请号:US15234403

    申请日:2016-08-11

    Abstract: A method for calculating a desired trajectory for a vehicle is provided. The vehicle is located at a position on a road bounded by two road edges, wherein the road edges are known at least in a region around the position of the vehicle. A spring-mass model is introduced, wherein the spring-mass model is used for calculating the desired trajectory, wherein the positions of the point masses are calculated for a rest state of the spring-mass model, and the calculated positions of the point masses are used as data points for the calculation of a curve connecting the point masses, whereby the curve represents the desired trajectory.

    Abstract translation: 提供了一种用于计算车辆的期望轨迹的方法。 车辆位于由两条道路边缘限定的道路上的位置,其中至少在车辆位置周围的区域中已知道路边缘。 引入弹簧质量模型,其中使用弹簧质量模型来计算所需的轨迹,其中针对弹簧质量模型的静止状态计算点块的位置,并且计算出的点块的位置 被用作用于计算连接点块的曲线的数据点,由此曲线表示期望的轨迹。

    COMPUTER-IMPLEMENTED METHOD FOR EDITING DATA OBJECT VARIANTS
    210.
    发明申请
    COMPUTER-IMPLEMENTED METHOD FOR EDITING DATA OBJECT VARIANTS 有权
    用于编辑数据对象变量的计算机实现方法

    公开(公告)号:US20170010887A1

    公开(公告)日:2017-01-12

    申请号:US14794331

    申请日:2015-07-08

    CPC classification number: G06F8/70 G05B19/41885 G06F9/4492 G06F9/4494

    Abstract: A computer-implemented method for editing data object variants of at least one software tool is described and presented, whereby the data object variants have at least one common software/hardware attribute and in each case a configuration of the attribute. It is possible to react to changing configurations of hardware attributes of different data object variants and thereby to changing matching groups during the editing of a data object variant in that for at least one attribute matching configurations of the attribute in different data object variants are captured and that for the attribute information on matching groups of data object variants is stored with the matching configurations of the attribute.

    Abstract translation: 描述和呈现用于编辑至少一个软件工具的数据对象变体的计算机实现的方法,由此数据对象变体具有至少一个公共软件/硬件属性,并且在每种情况下都是属性的配置。 可以对不同数据对象变体的硬件属性的变化配置作出反应,从而在数据对象变体的编辑期间改变匹配组,因为对于不同数据对象变体中的属性的匹配配置的至少一个属性被捕获, 对于与数据对象变体的匹配组的属性信息的存储与属性的匹配配置。

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