公开(公告)号：US20190325981A1

公开(公告)日：2019-10-24

申请号：US16388445

申请日：2019-04-18

Applicant: Silicon Motion, Inc.

Inventor： Yu-Hsuan CHENG

IPC: G11C29/42 ,  G11C29/24 ,  G06F3/06 ,  G11C29/00

Abstract: A data storage apparatus and a method for preventing data error using the same are provided. The data storage apparatus includes a memory and a memory controller. The memory includes a plurality of blocks. The memory controller is coupled to the memory and configured to perform the following operations: recording a read count of a target block of the memory; performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.

公开(公告)号：US20190324851A1

公开(公告)日：2019-10-24

申请号：US16048311

申请日：2018-07-29

Applicant: Silicon Motion Inc.

Inventor： Yu-Luen Wang

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  H03M13/00

Abstract: The present invention provides a decoding method, wherein the decoding method includes the steps of: reading a codeword from a flash memory module; and utilizing a parity check matrix to decode the codeword, wherein the parity check matrix includes a plurality of circulant permutation matrixes, and an order of a parallel calculation of the decoding step is less than a row number of any one of the circulant permutation matrixes.

公开(公告)号：US10437520B2

公开(公告)日：2019-10-08

申请号：US16012782

申请日：2018-06-20

Applicant: Silicon Motion Inc.

Inventor： Wei-Lun Yan ,  Ming-Yen Lin ,  Chin-Pang Chang

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56

Abstract: A method for performing writing management in a memory device, the memory device, and the controller thereof are provided. The method may include: writing first partial data of even-page data into a non-volatile (NV) memory; transmitting a first set of commands without a confirmation command to the NV memory, to write the first partial data and second partial data of the even-page data into an internal buffer within the NV memory; transmitting a second set of commands and the confirmation command to the NV memory, to write the first partial data and the second partial data into a block of the NV memory; writing third partial data of odd-page data into the NV memory; and writing the first and the second partial data into an even page of another block of the NV memory, and writing the third and fourth partial data into an odd page of this block.

公开(公告)号：US20190303299A1

公开(公告)日：2019-10-03

申请号：US16180251

申请日：2018-11-05

Applicant: Silicon Motion, Inc.

Inventor： Che-Jen SU

IPC: G06F12/1009

Abstract: A control unit for a data storage system is shown, which provides at least two buffers for updating mapping information through a host memory buffer HMB. A first buffer is provided for dynamic management of a physical-to-logical mapping table F2H that records a mapping relationship which maps a physical address within a target block to a logical address of a sector of user data stored at the physical address. The control unit performs reverse conversion on the mapping relationship to get reversed mapping information for the logical address and, accordingly, selects a target logical-to-physical mapping sub-table. A second buffer is provided to buffer the target logical-to-physical mapping sub-table when the target logical-to-physical mapping sub-table is read from the host memory buffer HMB. The control unit updates the target logical-to-physical mapping sub-table on the second buffer based on the reversed mapping information about the logical address.

公开(公告)号：US20190294499A1

公开(公告)日：2019-09-26

申请号：US16056555

申请日：2018-08-07

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C16/10 ,  G11C29/52

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method comprises: receiving data and a corresponding metadata from a host device; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data comprises the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.

公开(公告)号：US20190272116A1

公开(公告)日：2019-09-05

申请号：US16288611

申请日：2019-02-28

Applicant: SHENZHEN SHICHUANGYI ELECTRONICS CO., LTD ,  Silicon Motion, Inc.

Inventor： Huang-Zhong NI ,  Jun CHENG

IPC: G06F3/06

Abstract: A batch automatic test method and a batch automatic test device for solid state disks are provided. The batch automatic test method is used for testing a plurality of solid state disks by a batch automatic test device. The solid state disks are coupled to the batch automatic test device. The batch automatic test method includes the following steps. A plurality of buses of the batch automatic test device are scanned to mark the solid state disks and a system disk. A piece of disk information of each of the solid state disks is shown. Each of the pieces of the disk information includes a disk location of each of the solid state disks. A formatting procedure is synchronously performed on the solid state disks according to the disk locations. After performing the formatting procedure, a burn-in test procedure is automatically and synchronously performed on the solid state disks.

公开(公告)号：US10404283B2

公开(公告)日：2019-09-03

申请号：US15259065

申请日：2016-09-08

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: H03M13/37 ,  H03M13/09 ,  H03M13/15 ,  H03M13/00

Abstract: A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.

公开(公告)号：US10403386B2

公开(公告)日：2019-09-03

申请号：US15598239

申请日：2017-05-17

Applicant: Silicon Motion, Inc.

Inventor： Sheng Yuan Huang

IPC: G11C29/42 ,  G11C16/10 ,  G11C16/26 ,  G11C29/44 ,  G11C16/34 ,  G11C29/12

Abstract: A method for screening bad columns in a data storage medium includes steps of: writing predetermined data into at least one sample block; comparing the written data with the predetermined data to calculate numbers of error bits in the plurality of columns; defining an inspection window covering a portion of the columns; summing the numbers of error bits in the portion of columns in the inspection window to obtain a total number of error bits and determining whether the total number of error bits is greater than a number of correctable bits; if yes, determining a start point and a terminal point of a bad column interval in the inspection window, wherein the numbers of error bits in the columns between the start point and the terminal point are greater than a threshold of error bits; and labeling the columns in the bad column interval as bad columns.

公开(公告)号：US20190250854A1

公开(公告)日：2019-08-15

申请号：US16027387

申请日：2018-07-05

Applicant: Silicon Motion Inc.

Inventor： Kuan-Yu Ke

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: The present invention provides a system on chip (SoC), wherein the SoC comprises a first processor, a second processor and a memory. The memory stores a first parameter and a second parameter, wherein the first parameter is set by the first processor to indicate whether a specific region of the memory is locked or unlocked, and the second parameter is set by the first processor to indicate whether the specific region of the memory is locked or unlocked. In the operations of the SoC, before the first processor intends or prepares to access the specific region, the first processor refers to the second parameter to determine if the specific region is allowed to be accessed by the first processor.

公开(公告)号：US20190227894A1

公开(公告)日：2019-07-25

申请号：US16163831

申请日：2018-10-18

Applicant: Silicon Motion, Inc.

Inventor： Po-Yi SHIH

IPC: G06F11/22 ,  G06F11/07 ,  G06F9/26

Abstract: A system for testing a data storage device includes the data storage device, an electronic device and a computer device. The electronic device includes a host device coupled to the data storage device and communicating with the data storage device via an interface logic. The computer device is coupled to the electronic device and is configured to issue a plurality of commands to test the data storage device in a test procedure. When the electronic device has been successfully started up, the computer device issues a first command to the electronic device to trigger the electronic device to enter a hibernate mode. After waiting for a first predetermined period of time, the computer device issues a second command to the electronic device, so as to wake up the electronic device.