公开(公告)号：US10970446B1

公开(公告)日：2021-04-06

申请号：US15988448

申请日：2018-05-24

Applicant: Xilinx, Inc.

Inventor： Jeffrey H. Seltzer ,  Khang K. Dao ,  Sabyasachi Das

IPC: G06F30/3312 ,  G06F30/34 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F119/12

Abstract: The disclosed approaches process a circuit design having first attributes associated with two or more signals or with sources of the two or more signals. The first attributes specify identifier values. The elements of the circuit design are placed on a target integrated circuit (IC), and timing analysis of the circuit design is performed after placing the elements of the circuit design. In response to the first attributes of the two or more signals or sources specifying equivalent identifier values and a path of at least one of the two or more signals or sources being timing-critical, equal numbers of one or more pipeline registers are inserted on paths of the two or more signals or sources.

公开(公告)号：US10969821B2

公开(公告)日：2021-04-06

申请号：US15991179

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Ryan Kinnerk ,  Bob W. Verbruggen ,  John E. McGrath

IPC: G06F1/12 ,  G06F1/14 ,  G06F1/10

Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

公开(公告)号：US10963615B1

公开(公告)日：2021-03-30

申请号：US16399445

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Abhishek Joshi ,  Grigor S. Gasparyan

IPC: G06F30/394 ,  H03K19/1776 ,  H03K19/17736 ,  G06F30/33 ,  G06F30/327

Abstract: Some examples described herein relate to routing in routing elements. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network comprising switches interconnected in an array of data processing engines (DPEs), generate global routes of nets in the modeled communication network, generate detailed routes of the nets using the global routes, and translate the detailed routes to a file. Each of the switches has multiple input or output channels connected to another switch that are modeled as a single input or output edge, respectively, connected to the other switch. Each global route is generated through edge(s) of the switches. Each detailed route is generated comprising identifying one of the multiple input or output channels modeled by each edge through which the respective global route is generated.

公开(公告)号：US10963170B2

公开(公告)日：2021-03-30

申请号：US16262420

申请日：2019-01-30

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  David P. Schultz ,  Weiguang Lu ,  Michelle Zeng

IPC: G06F3/06

Abstract: Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.

公开(公告)号：US10951249B1

公开(公告)日：2021-03-16

申请号：US16830481

申请日：2020-03-26

Applicant: Xilinx, Inc.

Inventor： Hongzhi Zhao ,  Vince C Barnes ,  Xiaohan Chen ,  Hemang Parekh

IPC: H04B1/04 ,  H04W52/16

Abstract: A transmit circuit operated with time-interpolated digital pre-distortion (DPD) coefficients to improve adjacent channel power ratio (ACPR) performance during a power mode change is provided. The transmit circuit includes a DPD circuit configured to operate with a first DPD coefficient according to a first transmit power level of a transmit power amplifier of the transmit circuit. The transmit circuit further includes a DPD coefficient management engine configured to retrieve a second DPD coefficient corresponding to the second transmit power level. The transmit circuit further includes a DPD coefficient time-interpolation engine configured to compute a set of time-interpolated DPD coefficients corresponding to a set of time instants for a transient period when the transmit power amplifier is adapted to the second DPD coefficient.

公开(公告)号：US10949586B1

公开(公告)日：2021-03-16

申请号：US16918228

申请日：2020-07-01

Applicant: Xilinx, Inc.

Inventor： Jaipal R. Nareddy ,  Suman Kumar Timmireddy ,  Rahul Gupta

IPC: G06F30/327 ,  G06F30/394 ,  G06F115/02

Abstract: Approaches for post-synthesis insertion of debug cores include a programmed processor inputting data that identify signals of a synthesized circuit design to be probed and determining whether or not debug cores and interfaces needed to probe the signals are absent from the circuit design. The programmed processor creates, in response to determining that the debug cores and interfaces are absent, the debug cores and interfaces in the circuit design. The programmed processor couples the debug cores and interfaces to the signals in the circuit design and synthesizes the debug cores and interfaces created in the circuit design to create a modified circuit design. The method includes generating a circuit definition from the modified circuit design by the programmed processor, and implementing a circuit that operates according to the circuit definition.

公开(公告)号：US10924096B1

公开(公告)日：2021-02-16

申请号：US16808053

申请日：2020-03-03

Applicant: Xilinx, Inc.

Inventor： Gourav Modi ,  Chee Chong Chan ,  Azarudin Abdulla ,  Riyas Noorudeen Remla

IPC: H03K5/135 ,  H05K1/02 ,  G06F1/10 ,  H03K5/00

Abstract: Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.

公开(公告)号：US10917077B1

公开(公告)日：2021-02-09

申请号：US16694485

申请日：2019-11-25

Applicant: Xilinx, Inc.

Inventor： Ali Boumaalif ,  John E. McGrath

IPC: G06F1/03 ,  H03C3/00 ,  H03K5/00 ,  H03K4/08

Abstract: A device includes a plurality of phase accumulators, a multiplexer, and an oscillator. The plurality of phase accumulators is configured to receive a plurality of frequencies and generate a plurality of ramp signals. The multiplexer is configured to receive the plurality of ramp signals from the plurality of phase accumulators and to select one ramp signal from the plurality of ramp signals. The oscillator is configured to receive the one selected ramp signal and to generate one amplitude signal associated therewith. The plurality of phase accumulators continues generating their respective ramp signal. The multiplexer subsequent to selecting the one ramp signal is configured to select another ramp signal associated with another one phase accumulator of the plurality of phase accumulators. The oscillator is further configured to receive the selected another ramp signal and to generate another amplitude signal associated therewith.

公开(公告)号：US10909292B1

公开(公告)日：2021-02-02

申请号：US16276336

申请日：2019-02-14

Applicant: Xilinx, Inc.

Inventor： Pongstorn Maidee

IPC: G06F30/34 ,  H03K19/17728 ,  H03K19/173 ,  G06F30/394

Abstract: In an example, a configurable block for a programmable device of a plurality of programmable devices in an integrated circuit (IC) includes a first flip-flop having a data port coupled to an output of an interface block of the programmable device, a clock port coupled to a first clock input, and an output port coupled to a first output. The configurable block further includes a second flip-flop having a data port coupled to the output of the interface block, a clock port coupled to the first clock input, and an output port coupled to a second output, and a first multiplexer having a first input port coupled to the output port of the first flip-flop, and a second input port coupled to the output port of the second flip-flop. The configurable block further includes a third flip-flop having an input port coupled to an output of the first multiplexer, a clock port coupled to a second clock input, and an output port coupled to a third output.

公开(公告)号：US10902315B2

公开(公告)日：2021-01-26

申请号：US15600806

申请日：2017-05-22

Applicant: XILINX, INC.

Inventor： Shaoxia Fang ,  Lingzhi Sui ,  Qian Yu ,  Junbin Wang ,  Yi Shan

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/08 ,  G06N3/04

Abstract: The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer module, a convolution operation unit and a hybrid computation unit. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.