公开(公告)号：US10566447B2

公开(公告)日：2020-02-18

申请号：US15818438

申请日：2017-11-20

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/267 ,  H01L29/32 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Aspect ratio trapping is employed during fabrication of the transistor device on a silicon substrate. Homojunction and heterojunction devices are formed using III-V materials with appropriate bandgaps. The emitter of the device may be electrically connected by a lateral buried metal contact.

公开(公告)号：US10546857B2

公开(公告)日：2020-01-28

申请号：US15434753

申请日：2017-02-16

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/762

Abstract: A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.

公开(公告)号：US20190355830A1

公开(公告)日：2019-11-21

申请号：US15979557

申请日：2018-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Jeng-Bang Yau ,  Alexander Reznicek ,  Tak H. Ning

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L27/11521

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

公开(公告)号：US20190355722A1

公开(公告)日：2019-11-21

申请号：US16526320

申请日：2019-07-30

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06

Abstract: After forming a plurality of semiconductor fins that are separated from one another by trenches on a substrate, the semiconductor fins are fully or partially oxidized to provide semiconductor oxide portions. The volume expansion caused by the oxidation of the semiconductor fins reduces widths of the trenches, thereby providing narrowed trenches for formation of epitaxial semiconductor fins using aspect ratio trapping techniques.

公开(公告)号：US20190259756A1

公开(公告)日：2019-08-22

申请号：US16399405

申请日：2019-04-30

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC: H01L27/098 ,  H01L29/423 ,  H01L21/8232 ,  H01L29/66 ,  H01L29/808

Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.

公开(公告)号：US20190259750A1

公开(公告)日：2019-08-22

申请号：US16400133

申请日：2019-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/07 ,  H01L21/8234 ,  H01L29/66 ,  G11C7/06 ,  H01L29/78

Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.

公开(公告)号：US10360526B2

公开(公告)日：2019-07-23

申请号：US15221185

申请日：2016-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Keith A. Jenkins ,  Barry P. Linder

IPC: G06K9/00 ,  G06K9/62 ,  G06Q10/06

Abstract: A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.

公开(公告)号：US20190214309A1

公开(公告)日：2019-07-11

申请号：US16354885

申请日：2019-03-15

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L27/085 ,  H01L29/808

Abstract: Vertical MOSFET and JFET devices are incorporated on the same chip, enabling circuit designs that benefit from the simultaneous use of such devices. A fabrication method allows formation of the devices using a shared source/drain layer on a bulk semiconductor substrate.

公开(公告)号：US10347539B2

公开(公告)日：2019-07-09

申请号：US15967845

申请日：2018-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L29/165 ,  H01L29/08 ,  H01L21/308 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/033 ,  H01L21/768 ,  H01L29/161 ,  H01L29/66

Abstract: In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.

公开(公告)号：US20190206859A1

公开(公告)日：2019-07-04

申请号：US16298458

申请日：2019-03-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L27/06 ,  H01L21/8238

CPC classification number: H01L27/0617 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/42364 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7889

Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.