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    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    201.
    发明申请
    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220399357A1

    公开(公告)日：2022-12-15

    申请号：US17348021

    申请日：2021-06-15

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/538 ,  H01L21/768

    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an tipper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, an intervening-material layer vertically between the tipper and lower polysilicon-comprising layers. An upper intermediate layer is vertically between the upper polysilicon-comprising layer and the intervening-material layer. A lower intermediate layer is vertically between the lower polysilicon-comprising layer and the intervening-material layer. The lower intermediate layer and the upper intermediate layer comprise at least one of (a), (b), and (c), where (a): a hafnium oxide; (b): a bilayer comprising silicon nitride and comprising silicon dioxide positioned vertically relative one another, the silicon nitride in the bilayer being closer to the intervening-material layer than is the silicon dioxide in the bilayer; and (c): SiOxNy, where each of “x” and “y” is from 1 atomic percent to 90 atomic percent of the total of the Si, the O, and the N in the SiOxNy. Methods are disclosed.

    Memory array and a method used in forming a memory array
    202.
    发明授权
    Memory array and a method used in forming a memory array 有权

    公开(公告)号：US11527550B2

    公开(公告)日：2022-12-13

    申请号：US17177357

    申请日：2021-02-17

    Applicant: Micron Technology, Inc.

    Inventor： Changhan Kim ,  Richard J. Hill ,  John D. Hopkins ,  Collin Howder

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L21/28

    Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.

    MICROELECTRONIC DEVICES WITH TIER STACKS WITH VARIED TIER THICKNESSES, AND RELATED METHODS AND SYSTEMS
    203.
    发明申请
    MICROELECTRONIC DEVICES WITH TIER STACKS WITH VARIED TIER THICKNESSES, AND RELATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20220359539A1

    公开(公告)日：2022-11-10

    申请号：US17814765

    申请日：2022-07-25

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Nancy M. Lomeli

    IPC: H01L27/115

    Abstract: Microelectronic devices include a stack structure of vertically alternating insulative and conductive structures arranged in tiers. The insulative structures of a lower portion of the stack structure are thicker than the insulative structures of an upper portion. The conductive structures of the lower portion are as thick, or thicker, than the conductive structures of the upper portion. At least one feature may taper in width and extend vertically through the stack structure. The thicker insulative structures of the lower portion extend a greater lateral distance from the at least one feature than the lateral distance, from the at least one feature, extended by the thinner insulative structures of the upper portion. During methods of forming such devices, sacrificial structures are removed from an initial stack of alternating insulative and sacrificial structures, leaving gaps between neighboring insulative structures. Conductive structures are then formed in the gaps. Systems are also disclosed.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    205.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220328519A1

    公开(公告)日：2022-10-13

    申请号：US17850214

    申请日：2022-06-27

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/3215 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed and individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor material between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material that is laterally-between the horizontally-elongated lines. After the horizontally-elongated lines are formed, conductive material of a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, Other embodiments, including structure independent of method, are disclosed.

    MICROELECTRONIC DEVICES INCLUDING AN INTERDECK REGION BETWEEN DECK STRUCTURES, AND RELATED ELECTRONIC DEVICES
    209.
    发明申请
    MICROELECTRONIC DEVICES INCLUDING AN INTERDECK REGION BETWEEN DECK STRUCTURES, AND RELATED ELECTRONIC DEVICES 有权

    公开(公告)号：US20220301860A1

    公开(公告)日：2022-09-22

    申请号：US17804978

    申请日：2022-06-01

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Damir Fazil

    IPC: H01L21/02 ,  H01L21/311

    Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.

    Devices comprising floating gate materials, tier control gates, charge blocking materials, and channel materials
    210.
    发明授权
    Devices comprising floating gate materials, tier control gates, charge blocking materials, and channel materials 有权

    公开(公告)号：US11411085B2

    公开(公告)日：2022-08-09

    申请号：US16795176

    申请日：2020-02-19

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.

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