公开(公告)号：US20140035009A1

公开(公告)日：2014-02-06

申请号：US14048923

申请日：2013-10-08

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L29/04

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract translation: 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US08021940B2

公开(公告)日：2011-09-20

申请号：US11968099

申请日：2007-12-31

Applicant: Matthew V. Metz ,  Mark L. Doczy ,  Gilbert Dewey ,  Jack Kavalieros

Inventor： Matthew V. Metz ,  Mark L. Doczy ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/324 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/785

Abstract: Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air.

Abstract translation: 描述形成微电子结构的方法。 那些方法可以包括在衬底上形成栅极电介质层，在栅极电介质层上形成金属栅极层，然后在原位在金属栅极层上形成多晶硅层，其中金属栅极层不暴露于空气中。

公开(公告)号：US20110156098A1

公开(公告)日：2011-06-30

申请号：US13016888

申请日：2011-01-28

Applicant: Prashant Majhi ,  Jack Kavalieros ,  Wilman Tsai

Inventor： Prashant Majhi ,  Jack Kavalieros ,  Wilman Tsai

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L29/7782 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02532 ,  H01L29/1075

Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.

Abstract translation: 本发明的实施例描述了具有缓冲结构的半导体器件和制造缓冲结构的方法。 缓冲结构形成在衬底和量子阱层之间，以防止由于晶格失配而引起的衬底和量子阱层中的缺陷。 缓冲结构包括形成在基板上的第一缓冲层，形成在第一缓冲层上的多个阻挡构件和形成在多个阻挡构件上的第二缓冲器。 多个阻挡构件防止第二缓冲层直接沉积在整个第一缓冲层上，以便最小化晶格失配并防止第一和第二缓冲层中的缺陷。

公开(公告)号：US07902058B2

公开(公告)日：2011-03-08

申请号：US10953295

申请日：2004-09-29

Applicant: Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Brian S. Doyle

Inventor： Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Brian S. Doyle

IPC: H01L21/8238

CPC classification number: H01L21/28079 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.

Abstract translation: 在金属栅极替换工艺中，可以在NMOS和PMOS晶体管的沟道中选择性地诱发应变。 例如，可以使用具有比衬底更高的热膨胀系数的材料来形成PMOS晶体管的栅电极。 可以使用具有比基板的热膨胀系数更低的热膨胀系数的材料来形成NMOS晶体管的栅电极。

公开(公告)号：US20110018063A1

公开(公告)日：2011-01-27

申请号：US12895954

申请日：2010-10-01

Applicant: Brian Doyle ,  Titash Rakshit ,  Jack Kavalieros

Inventor： Brian Doyle ,  Titash Rakshit ,  Jack Kavalieros

IPC: H01L29/78

CPC classification number: H01L29/7855 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提高多栅极器件性能的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20100285279A1

公开(公告)日：2010-11-11

申请号：US11968091

申请日：2007-12-31

Applicant: Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Robert Chau

Inventor： Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Robert Chau

IPC: B32B3/10 ,  B05D3/10 ,  B05D1/36

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  Y10T428/24612

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括在纳点物质上形成第一块，在第一块上形成第一间隔物，去除第一块以形成自由间隔物，去除纳米点材料的暴露部分，然后除去自由基间隔物以形成纳米线， 在与所述纳米线的长度成一定角度地形成第二块，在所述第二块上形成第二间隔物，通过去除所述第二块在所述纳米线上形成第二自由间隔物，以及去除所述纳米线的暴露部分，然后除去所述第二自由基 形成有序阵列的纳米点。

公开(公告)号：US07825481B2

公开(公告)日：2010-11-02

申请号：US12343400

申请日：2008-12-23

Applicant: Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L27/088

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract translation: 描述具有窄带隙半导体源极/漏极区域的晶体管。 晶体管包括形成在形成于硅层上的栅介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上，其中所述一对源极/漏极区域包括形成在栅电极的相对侧上的硅层中的窄带隙半导体膜。

公开(公告)号：US20100219456A1

公开(公告)日：2010-09-02

申请号：US12781084

申请日：2010-05-17

Applicant: Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Robert S. Chau

Inventor： Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Robert S. Chau

IPC: H01L29/78 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L27/092 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.

Abstract translation: 在金属栅极更换工艺中，可以形成至少两个多晶硅层或其它材料的堆叠。 侧壁间隔物可以形成在堆叠上。 然后可以将堆叠平坦化。 接下来，可以选择性地去除堆叠的上层。 然后，可以选择性地去除侧壁间隔物的暴露部分。 最后，堆叠的下部可以被去除以形成可以用金属替代物填充的T形沟槽。

公开(公告)号：US20100155954A1

公开(公告)日：2010-06-24

申请号：US12317180

申请日：2008-12-18

Applicant: Niloy Mukherjee ,  Matt Metz ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S. Chau

Inventor： Niloy Mukherjee ,  Matt Metz ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S. Chau

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/76814

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括在设置在基板上的层间电介质（ILD）中形成接触开口，其中暴露源极/漏极接触区域，在源极/漏极接触区域上形成稀土金属层，形成过渡金属层 在稀土金属层上; 并对稀土金属层和过渡金属层退火以形成金属硅化物堆叠结构。

公开(公告)号：US07718479B2

公开(公告)日：2010-05-18

申请号：US10925468

申请日：2004-08-25

Applicant: Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Robert S. Chau

Inventor： Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Robert S. Chau

IPC: H01L21/338

CPC classification number: H01L27/092 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.

Abstract translation: 在金属栅极更换工艺中，可以形成至少两个多晶硅层或其它材料的堆叠。 侧壁间隔物可以形成在堆叠上。 然后可以将堆叠平坦化。 接下来，可以选择性地去除堆叠的上层。 然后，可以选择性地去除侧壁间隔物的暴露部分。 最后，堆叠的下部可以被去除以形成可以用金属替代物填充的T形沟槽。