公开(公告)号：US10179036B2

公开(公告)日：2019-01-15

申请号：US15946984

申请日：2018-04-06

Applicant: Jong Ho Lee

Inventor： Jong Ho Lee

IPC: A61C3/00 ,  A61C7/22 ,  A61C7/20 ,  A61C7/28

Abstract: Disclosed is an archwire with a varied cross section which is formed integrally with a hook. The archwire includes a customized archwire body corresponding to a setup model of patient's teeth, and the hook which is formed integrally with the archwire body. The archwire body is formed in such a way that at least one region has a cross section different from that of another region.

公开(公告)号：US20180206941A1

公开(公告)日：2018-07-26

申请号：US15744777

申请日：2015-11-18

Applicant: JONG HO LEE

Inventor： JONG HO LEE

IPC: A61C7/02 ,  A61C7/20 ,  A61C7/00

CPC classification number: A61C7/02 ,  A61C7/002 ,  A61C7/12 ,  A61C7/20

Abstract: A customized orthodontic archwire fabrication kit and a method of fabricating an orthodontic archwire using the same are disclosed. The orthodontic archwire fabrication kit according to the present disclosure comprises: a jig base formed by perforating the pairs of inner fastening holes and outer fastening holes corresponding to the positions of teeth on a dental setup model of a patient; a jig comprising at one end a first head through which a first through hole is penetrated, at the other end a second head through which a second through hole is penetrated, and a body connecting the first head and the second head and having a wire ligation slot recessed on a portion of the top of the body; a fixing screw corresponding to the dimensions of the first through hole and inner fastening hole; and a fixture corresponding to the dimensions of the second through hole and outer fastening hole. By applying heat in a furnace after the nitinol wire is ligated to and fixed in the jig's wire ligation slot, a custom orthodontic archwire will be created.

公开(公告)号：US20170313375A1

公开(公告)日：2017-11-02

申请号：US15529753

申请日：2015-05-19

Applicant: Jong-ho LEE

Inventor： Jong-ho LEE

IPC: B62K5/10 ,  B62M1/28 ,  B62K5/02

CPC classification number: B62K5/10 ,  B62K5/02 ,  B62M1/28

Abstract: The present disclosure provides a tilting-capable three-wheeled boarding vehicle comprising: a steering-assembly configured to enable steering and tilting of the vehicle; a tilting-capable assembly including one driving wheel and a rotatable elongate body extending from the steering-assembly toward driven-wheels; a non-tilted assembly including a non-rotatable elongate body, the two driven wheels, a shaft connecting the two driven wheels to each other, and a first support bar extending perpendicularly to the non-rotatable elongate body, wherein the rotatable elongate body is rotatably coupled to the non-rotatable elongate body; and a vertically-movable elongate assembly pivotally coupled, at one end thereof, to the rotatable elongate body and contacting, at the other end thereof, the first support bar during downward movement thereof, wherein the vertically-movable elongate assembly is configured to vertically move by pedaling forces from a user.

公开(公告)号：US09564200B2

公开(公告)日：2017-02-07

申请号：US13010360

申请日：2011-01-20

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/66 ,  G11C11/403 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: G11C11/403 ,  H01L27/10876 ,  H01L29/42392 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/78642 ,  H01L29/78648

Abstract: A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes: a semiconductor body, source and drain formed in a semiconductor pillar; a gate insulating layer formed on a surface of the semiconductor body; a gate electrode formed on a surface of the gate insulating layer. The gate electrode includes a first gate electrode and a second gate electrode being electrically connected with the first gate electrode. The first gate electrode has a work function higher than that of the second gate electrode. Accordingly, the gate induced drain leakage (GIDL) can be reduced, so that an off-state leakage current can be greatly reduced.

Abstract translation: 提供了具有低泄漏电流的柱型场效应晶体管。 柱型场效应晶体管包括：半导体本体，形成在半导体柱中的源极和漏极; 形成在所述半导体主体的表面上的栅极绝缘层; 形成在栅极绝缘层的表面上的栅电极。 栅电极包括与第一栅电极电连接的第一栅电极和第二栅电极。 第一栅电极具有比第二栅电极高的功函数。 因此，可以减小栅极感应漏极泄漏（GIDL），从而可以大大降低截止状态的漏电流。

公开(公告)号：US20160315087A1

公开(公告)日：2016-10-27

申请号：US15069920

申请日：2016-03-14

Applicant: Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

Inventor： Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

IPC: H01L27/092 ,  H01L29/43 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

公开(公告)号：US20160163377A1

公开(公告)日：2016-06-09

申请号：US14959003

申请日：2015-12-04

Applicant: Tae Young OH ,  Su Yeon DOO ,  Seung Hoon OH ,  Jong Ho LEE ,  Kwang Il PARK

Inventor： Tae Young OH ,  Su Yeon DOO ,  Seung Hoon OH ,  Jong Ho LEE ,  Kwang Il PARK

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/40618

Abstract: A method of operating a semiconductor memory device is provided as follows. The semiconductor memory device receive a bank address for a first bank including a first word line, a second word line and a third word line. The semiconductor memory device receive a first row address to activate the first world line for a read operation or a write operation. The semiconductor memory device generates a second row address to refresh a plurality of memory cells associated with the second word line.

Abstract translation: 如下提供操作半导体存储器件的方法。 半导体存储器件接收包括第一字线，第二字线和第三字线的第一存储体的存储体地址。 半导体存储器件接收第一行地址以激活用于读取操作或写入操作的第一世界线。 半导体存储器件产生第二行地址以刷新与第二字线相关联的多个存储单元。

公开(公告)号：US09151740B2

公开(公告)日：2015-10-06

申请号：US13614570

申请日：2012-09-13

Applicant: Jong-ho Lee ,  Jun-mo Park

Inventor： Jong-ho Lee ,  Jun-mo Park

IPC: G01N27/26 ,  G01N33/487 ,  B82Y5/00 ,  B82Y40/00 ,  B82Y15/00

CPC classification number: G01N33/48721 ,  B82Y5/00 ,  B82Y15/00 ,  B82Y40/00

Abstract: A nanopore device comprising a channel unit comprising a micro channel defined by a bottom surface and an insulator lateral wall; and a cover unit covering the micro channel, wherein the cover unit comprises a nanopore extending through the cover unit and connected to the micro channel; a first source/drain electrode disposed on an upper surface of the cover unit and adjacent to an inlet of the nanopore; an opening extending through the cover unit and connected to the micro channel; and a second source/drain electrode disposed on the upper surface of the cover unit and adjacent to the opening; as well as a method for fabricating and using the device.

Abstract translation: 一种纳米孔装置，其包括通道单元，该通道单元包括由底表面和绝缘体侧壁限定的微通道; 以及覆盖所述微通道的盖单元，其中所述盖单元包括延伸穿过所述盖单元并连接到所述微通道的纳米孔; 第一源极/漏电极，设置在所述盖单元的上表面上并且邻近所述纳米孔的入口; 一个延伸穿过盖单元并连接到微通道的开口; 以及设置在盖单元的上表面上且与开口相邻的第二源/漏电极; 以及制造和使用该装置的方法。

公开(公告)号：US09092456B2

公开(公告)日：2015-07-28

申请号：US13545085

申请日：2012-07-10

Applicant: Jaewon Kim ,  Ig Jae Kim ,  Sang Chul Ahn ,  Jong-Ho Lee

Inventor： Jaewon Kim ,  Ig Jae Kim ,  Sang Chul Ahn ,  Jong-Ho Lee

IPC: G06T3/40 ,  G06F17/30

CPC classification number: G06F17/30247 ,  G06F17/30265 ,  G06T3/4053

Abstract: A method and system for reconstructing an image displayed on an electronic device connected to a network, to be a high resolution image. The method of reconstructing a selected area of the image displayed on the electronic device connected to a network, to be a high resolution image, includes: receiving a request to expand the selected area; collecting images including the selected area from the Internet; correcting the selected area to have a high resolution while expanding the selected area based on the collected images; and displaying the image expanded to have a high resolution on the electronic device.

Abstract translation: 一种用于重建显示在连接到网络的电子设备上的图像的方法和系统，以成为高分辨率图像。 将显示在连接到网络的电子设备上的图像的选定区域重建为高分辨率图像的方法包括：接收扩展所选区域的请求; 从互联网收集包括所选区域的图像; 基于所收集的图像，将所选择的区域校正为具有高分辨率，同时扩展所选择的区域; 并且在电子设备上显示被扩展为具有高分辨率的图像。

公开(公告)号：US08947932B2

公开(公告)日：2015-02-03

申请号：US12708342

申请日：2010-02-18

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L27/108 ,  H01L29/78

CPC classification number: H01L29/7841 ,  H01L27/108 ,  H01L27/10802

Abstract: Provided is a one-transistor (1T) floating-body DRAM cell device including a substrate; a gate stack which is formed on the substrate; a control electrode which is disposed on the substrate and of which some or entire portion is surrounded by the gate stack; a semiconductor layer which is formed on the gate stack; a source and a drain which are formed in the surface of the semiconductor layer and of which lower surfaces are not in contact with the gate stack; a gate insulating layer which is formed on the semiconductor layer; and a gate electrode which is formed on the gate insulating layer, wherein the remaining portion of the semiconductor layer excluding the source and the drain is configured as a floating body. The miniaturization characteristic and performance of a MOS-based DRAM cell device can be improved, and a memory capacity can be increased.

Abstract translation: 提供了一种包括衬底的单晶体管（1T）浮体DRAM单元器件; 形成在基板上的栅极堆叠; 控制电极，其设置在所述基板上，并且其一些或全部部分被所述栅极堆叠包围; 形成在栅叠层上的半导体层; 源极和漏极，其形成在半导体层的表面中并且其下表面不与栅极堆叠接触; 形成在半导体层上的栅极绝缘层; 以及形成在所述栅极绝缘层上的栅极，其中，除了所述源极和漏极之外的所述半导体层的剩余部分被构造为浮体。 可以提高基于MOS的DRAM单元装置的小型化特性和性能，并且可以提高存储容量。

公开(公告)号：US08836189B2

公开(公告)日：2014-09-16

申请号：US13315565

申请日：2011-12-09

Applicant: Jong Ho Lee

Inventor： Jong Ho Lee

IPC: H02K7/08 ,  G11B19/20 ,  F16C17/10 ,  F16C33/74

CPC classification number: H02K7/085 ,  F16C17/107 ,  F16C33/745 ,  F16C2370/12 ,  G11B19/2036

Abstract: There is provided a spindle motor including: a sleeve rotatably supporting a shaft and having an insertion groove provided in a top surface thereof; and a rotor case mounted on a top end of the shaft and including a protruding wall part inserted into the insertion groove, wherein a lubricant, provided to generate a dynamic pressure when the shaft rotates, forms an interface with air in a clearance formed by the protruding wall part and the insertion groove.

Abstract translation: 提供了一种主轴电动机，其包括：可旋转地支撑轴并具有设置在其顶表面中的插入槽的套筒; 以及转子壳体，其安装在所述轴的顶端，并且包括插入到所述插入槽中的突出壁部分，其中设置成当所述轴旋转时产生动态压力的润滑剂与由所述轴的旋转形成的间隙中的空气形成界面， 突出部分和插入槽。