公开(公告)号：US10599802B2

公开(公告)日：2020-03-24

申请号：US16010536

申请日：2018-06-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Or Davidi ,  Roy Armoni

IPC: G06F17/50

Abstract: An apparatus for IC design includes a memory configured to store an original Register Transfer Level (RTL) model, a corrected RTL model, and a translation of the original RTL model into a netlist. A processor is configured to identify in the original RTL model a flip-flop having a next-state function that is not equivalent to a corresponding next-state function of a corresponding flip-flop in the Corrected RTL model, to find a wire, which is the earliest ancestor of the flip-flop for which there is no equivalence between the original RTL model and the corrected RTL model, to check whether the wire has an equivalent net in the netlist, to identify, upon finding that the wire has no equivalent net, one or more ancestors of the wire, which do have equivalent nets in the netlist, and to modify the netlist to match the corrected RTL model.

公开(公告)号：US20200014918A1

公开(公告)日：2020-01-09

申请号：US16291023

申请日：2019-03-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Kobi Pines ,  Noam Bloch ,  Erez Yaacov ,  Ariel Naftali Cohen

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/139

Abstract: A system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each the block of the second plurality of blocks, to produce a score of result blocks based on similarity of each the block in each frame to be encoded to every block of the reference frame, and a displacement vector. Related apparatus and methods are also provided.

公开(公告)号：US10528519B2

公开(公告)日：2020-01-07

申请号：US15584327

申请日：2017-05-02

Applicant: Mellanox Technologies Ltd.

Inventor： Mark Rosenbluth

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F15/80

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.

公开(公告)号：US10522977B1

公开(公告)日：2019-12-31

申请号：US16179244

申请日：2018-11-02

Applicant: Mellanox Technologies, Ltd.

Inventor： Elad Mentovich ,  Itshak Kalifa ,  Sylvie Rockman ,  Eyal Waldman ,  Alon Webman ,  Isabelle Cestier

IPC: H01S5/42 ,  H01S5/022 ,  H04J14/02 ,  H04B10/25 ,  H04B10/50 ,  G02B6/43 ,  G02B6/28 ,  H04B10/40

Abstract: An electro-optical link is provided. In an example embodiment, the electro-optical link includes a number of vertical cavity surface emitting lasers (VCSELs); one or more drivers that operate the VCSELs such that each of the VCSELs selectively emits an optical signal; one or more multiplexers that multiplex a number of optical signals into an optical fiber, each optical signal emitted by one of the VCSELs; and one or more optical fibers. At least two optical signals are multiplexed into each optical fiber of the one or more optical fibers. In some example configurations eight or sixteen optical signals are multiplexed into one optical fiber.

公开(公告)号：US10521283B2

公开(公告)日：2019-12-31

申请号：US15446004

申请日：2017-03-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Shahaf Shuler ,  Noam Bloch ,  Gil Bloch

IPC: G06F9/54

Abstract: An MPI collective operation carried out in a fabric of network elements by transmitting MPI messages from all the initiator processes in an initiator node to designated ones of the responder processes in respective responder nodes. Respective payloads of the MPI messages are combined in a network interface device of the initiator node to form an aggregated MPI message. The aggregated MPI message is transmitted through the fabric to network interface devices of responder nodes, disaggregating the aggregated MPI message into individual messages, and distributing the individual messages to the designated responder node processes.

公开(公告)号：US10473857B2

公开(公告)日：2019-11-12

申请号：US16031428

申请日：2018-07-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Yaakov Gridish ,  Eran Aharon ,  Elad Mentovich ,  Sylvie Rockman

IPC: G02B6/14 ,  G02B6/028 ,  G02B6/26 ,  G02B6/12

Abstract: A waveguide having a gradient-index (GRIN) waveguide lateral coupler is provided. In an example embodiment, the waveguide comprises an active region. The refractive index profile of the active region is non-constant.

公开(公告)号：US20190332291A1

公开(公告)日：2019-10-31

申请号：US15963236

申请日：2018-04-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Shahar ,  Peter Paneah ,  Maxim ZABOROV

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.

公开(公告)号：US20190312413A1

公开(公告)日：2019-10-10

申请号：US15944955

申请日：2018-04-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Alexei Sirbu ,  Vladimir Iakovlev ,  Yuri Berk ,  Elad Mentovich

IPC: H01S5/42 ,  H01S5/022 ,  H01S5/183 ,  H01S5/187 ,  H01S5/042 ,  H01S5/028 ,  H01S5/40 ,  H01S5/343

Abstract: A vertical-cavity surface-emitting laser (VCSEL), substrate emitting VCSEL, and multi-beam emitting device and corresponding manufacturing processes are provided. An example VCSEL comprises a substrate having a first surface and a second surface; an output coupling mirror disposed on the second surface of the substrate; a high reflectivity mirror; and an active cavity material structure disposed between the output coupling mirror and the high reflectivity mirror. The active cavity material structure comprises a first current-spreading layer, a second current-spreading layer, an active region disposed between the first current-spreading layer and the second current-spreading layer, and a tunnel junction overgrown by the second current spreading layer, wherein the tunnel junction is disposed adjacent the active region. The VCSEL is configured to emit radiation outward through the first surface of the substrate.

公开(公告)号：US20190310945A1

公开(公告)日：2019-10-10

申请号：US15947816

申请日：2018-04-08

Applicant: Mellanox Technologies, Ltd.

Inventor： Ahmad Atamlh ,  Ofir Arkin ,  Peter Paneah

IPC: G06F12/10 ,  G06F13/10 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42

Abstract: An apparatus includes an interface and memory acquisition circuitry. The interface is configured to communicate over a bus operating in accordance with a bus protocol, which supports address-translation transactions that translate between bus addresses in an address space of the bus and physical memory addresses in an address space of a memory. The memory acquisition circuitry is configured to read data from the memory by issuing over the bus, using the bus protocol, one or more requests that (i) specify addresses to be read in terms of the physical memory addresses, and (ii) indicate that the physical memory addresses in the requests have been translated from corresponding bus addresses even though the addresses were not obtained by any address-translation transaction over the bus.

公开(公告)号：US10382350B2

公开(公告)日：2019-08-13

申请号：US15701459

申请日：2017-09-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Dror Bohrer ,  Noam Bloch ,  Lior Narkis ,  Hillel Chapman ,  Gilad Hammer

IPC: G06F9/455 ,  H04L12/741 ,  H04L12/813 ,  H04L12/863 ,  H04L12/931

Abstract: Network interface apparatus includes a host interface and a network interface, which receives packets in multiple packet flows destined for one or more virtual machines running on a host processor. Packet processing circuitry receives a first instruction from the host processor to offload preprocessing of the data packets in a specified flow in accordance with a specified rule, and initiates preprocessing of the data packets while writing one or more initial data packets from the specified flow to a temporary buffer. Upon subsequently receiving a second instruction to enable the specified rule, the initial data packets are delivered from the temporary buffer, after preprocessing by the packet processing circuitry, directly to a virtual machine to which the specified flow is destined, followed by preprocessing and delivery of subsequent data packets in the specified flow to the virtual machine.