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公开(公告)号：US20220200607A1
公开(公告)日：2022-06-23
申请号：US17519122
申请日：2021-11-04
Applicant: STMicroelectronics International N.V.
Inventor： Ankit GUPTA
Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.
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公开(公告)号：US20220173736A1
公开(公告)日：2022-06-02
申请号：US17531654
申请日：2021-11-19
Applicant: STMicroelectronics International N.V.
Inventor： Vaibhav Garg , Abhishek Jain , Anand Kumar
IPC: H03K17/687
Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.
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公开(公告)号：US20220172751A1
公开(公告)日：2022-06-02
申请号：US17534136
申请日：2021-11-23
Applicant: STMicroelectronics International N.V.
Inventor： Shivam KALLA , Vikas RANA
Abstract: An integrated circuit includes a non-volatile memory, a charge pump that generates high voltages for programming operations of the non-volatile memory array, and a charge pump regulator that controls a slew rate of the charge pump. The charge pump regulator generates a sense current indicative of the slew rate and adjusts a frequency of a clock signal provided to the charge pump based on the sense current.
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公开(公告)号：US20220165317A1
公开(公告)日：2022-05-26
申请号：US17542203
申请日：2021-12-03
Inventor： Vivek TYAGI , Vikas RANA , Chantal AURICCHIO , Laura CAPECCHI
IPC: G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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215.发明申请公开(公告)号：US20220158552A1
公开(公告)日：2022-05-19
申请号：US17494244
申请日：2021-10-05
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA
Abstract: The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.
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Patent Agency Ranking
公开(公告)号：US20220123699A1
公开(公告)日：2022-04-21
申请号：US17565288
申请日：2021-12-29
Applicant: STMicroelectronics International N.V.
Inventor： Prashant Singh
IPC: H03F3/45
Abstract: A squelch detection device is provided. The squelch detection device receives first and second input signals and first and second threshold voltages. The squelch detection device determines a first common mode of the first and second input signals and a second common mode of the first and second threshold voltages. The squelch detection device averages the first common mode with the second common mode to produce an average common mode and sets the first common mode of the first and second input signals to the average common mode. The squelch detection device sets the second common mode of the first and second threshold voltages to the average common mode and determines a state of a squelch signal, indicative of whether the first and second input signals are attributable to noise, based on the first and second input signals and the first and second threshold voltages.
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公开(公告)号：US20220122682A1
公开(公告)日：2022-04-21
申请号：US17567481
申请日：2022-01-03
Applicant: STMicroelectronics International N.V.
Inventor： Vivek Mohan Sharma , Deepak Baranwal , Nicolas Bernard Grossier , Samiksha Agarwal
Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.
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公开(公告)号：US11305534B2
公开(公告)日：2022-04-19
申请号：US16945465
申请日：2020-07-31
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Simon Dodd , David S. Hunt , Joseph Edward Scheffelin , Dana Gruenbacher , Stefan H. Hollinger , Uwe Schober , Peter Janouch
Abstract: The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support with respect to a direction of ejection of the nozzles, and a semi-flexible support or semi-rigid support that allow the electrical contacts to be moved with respect to a direction of ejection of the nozzles. The semi-flexible and semi-rigid supports allow the die to be up to and beyond a 90 degree angle with respect to a plane of the electrical contacts. The different supports allow for a variety of positions of the microfluidic die with respect to a position of the electrical contacts.
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219.发明申请公开(公告)号：US20220068400A1
公开(公告)日：2022-03-03
申请号：US17006510
申请日：2020-08-28
Inventor： Marco PASOTTI , Dario LIVORNESI , Roberto BREGOLI , Vikas RANA , Abhishek MITTAL
Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.
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公开(公告)号：US20220057446A1
公开(公告)日：2022-02-24
申请号：US17001131
申请日：2020-08-24
Applicant: STMicroelectronics International N.V.
Inventor： Pravesh Kumar Saini , Shashawat
IPC: G01R31/28 , G01R31/52 , H03K19/20 , H03K17/687
Abstract: An on chip leakage-current detection device including a first inverter where the magnitude of delay of the output signal of the first inverter is determined by a leakage current of a target device. The leakage-current detection device further includes: a capacitor that is charged by the output signal of the first inverter; a second inverter coupled to capacitor that switches states when the capacitor is charged to a switching level; an odd number of additional inverters coupled in a sequence with a second-inverter output. The output of the leakage-current detection device has a frequency proportional to the leakage of the target device.
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