公开(公告)号：US20020126548A1

公开(公告)日：2002-09-12

申请号：US10044307

申请日：2001-10-26

Applicant: STMicroelectronics S.A.

Inventor： Jerome Ciavatti

IPC: H01L021/8242

CPC classification number: H01L21/76897 ,  H01L27/10888 ,  Y10S438/954

Abstract: A method for manufacturing a DRAM cell including two active word lines having a drain region and distinct source regions, including, after the forming of insulated conductive lines, the steps of: depositing a first, then a second selectively etchable insulating layers; etching the second insulating layer to only maintain it above conductive lines; depositing and leveling a third insulating layer selectively etchable with respect to at least the second insulating layer; opening the first and third insulating layers to expose the drain region and an insulating trench; filling the previously-formed opening with a conductive material; polishing the entire structure; and depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.

Abstract translation: 一种用于制造DRAM单元的方法，所述DRAM单元包括具有漏极区和不同源极区的两个有源字线，包括在形成绝缘导线之后的步骤：沉积第一，然后第二可选择蚀刻的绝缘层; 蚀刻第二绝缘层以仅将其保持在导电线之上; 沉积和调平相对于至少第二绝缘层可选择性蚀刻的第三绝缘层; 打开第一和第三绝缘层以暴露漏极区域和绝缘沟槽; 用导电材料填充先前形成的开口; 抛光整个结构; 以及沉积相对于所述第三绝缘层可选择性蚀刻的第四绝缘层。

公开(公告)号：US20020125866A1

公开(公告)日：2002-09-12

申请号：US10052209

申请日：2002-01-16

Applicant: STMicroelectronics, S.A.

Inventor： Cecile Hamon ,  Christophe Bernard ,  Alexandre Pons

IPC: G05F001/40

CPC classification number: G05F1/46 ,  H03K17/122

Abstract: A voltage regulator having an output terminal provided for being connected to a load, including an amplifier having its inverting input connected to a reference voltage, and its non-inverting input connected to the output terminal, a charge capacitor arranged between the output terminal and a first supply voltage, first and second voltage-controlled switches each arranged to connect a second supply voltage and the output terminal, and a control means adapted to providing a voltage depending on the output voltage of the amplifier, on the one hand, to the gate of the first switch and, on the other hand, when the current flowing through the first switch reaches a predetermined threshold, to the gate of the second switch.

Abstract translation: 一种电压调节器，其具有设置用于连接到负载的输出端子，包括具有连接到参考电压的反相输入的放大器，以及连接到输出端子的其非反相输入端，布置在输出端子和 第一电源电压，第一和第二电压控制开关，每个被布置成连接第二电源电压和输出端子;以及控制装置，一方面提供取决于放大器的输出电压的电压， 并且另一方面，当流过第一开关的电流达到预定阈值时，到达第二开关的栅极。

公开(公告)号：US20020109491A1

公开(公告)日：2002-08-15

申请号：US09953071

申请日：2001-09-14

Applicant: STMicroelectronics S.A.

Inventor： Edith Kussener

IPC: G05F003/16

CPC classification number: G05F3/30 ,  Y10S323/907

Abstract: A regulated voltage generator provides different regulated voltages to an integrated circuit. The regulated voltage generator includes a bandgap reference circuit and at least one gain stage connected to an output thereof. The output voltage of the bandgap reference circuit varies as a function of temperature to compensate for variations in the gain stage made up of first and second transistors. A regulated voltage output by the regulated voltage generator is independent of temperature and of the supply voltage. The value of the regulated voltage is adjusted via a load resistor and via the first and second transistors along with an output transistor of the bandgap reference circuit.

Abstract translation: 调节电压发生器为集成电路提供不同的调节电压。 调节电压发生器包括带隙参考电路和连接到其输出的至少一个增益级。 带隙参考电路的输出电压作为温度的函数而变化，以补偿由第​​一和第二晶体管构成的增益级的变化。 调节电压发生器的稳压输出与温度和电源电压无关。 调节电压的值通过负载电阻器和第一和第二晶体管以及带隙基准电路的输出晶体管进行调整。

公开(公告)号：US20020099890A1

公开(公告)日：2002-07-25

申请号：US09989317

申请日：2001-11-20

Applicant: STMicroelectronics S.A.

Inventor： Xavier Mariaud ,  Daniel Klingelschmidt

IPC: G06F013/00

CPC classification number: G06F13/24 ,  G06F13/426

Abstract: A circuit is provided for reducing losses of the start of a new message caused by the microcontroller of a slave apparatus being unavailable. The circuit generates an interruption signal when the slave apparatus has received and acknowledged a start of a new message but the microcontroller is unavailable because it is processing a preceding message or an application of the slave apparatus.

Abstract translation: 提供了一种用于减少由不可用的从设备的微控制器引起的新消息的开始损失的电路。 当从设备已经接收并确认新消息的开始但是微控制器由于处理先前的消息或从设备的应用而不可用时，电路产生中断信号。

公开(公告)号：US20020094678A1

公开(公告)日：2002-07-18

申请号：US10044402

申请日：2002-01-11

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Yvon Gris

IPC: C21D001/00

CPC classification number: H01L21/76235 ,  H01L21/02667 ,  H01L21/2022

Abstract: An initial single-crystal substrate 1 having, locally and on the surface, at least one discontinuity in the single-crystal lattice is formed. The initial substrate is recessed at the discontinuity. The single-crystal lattice is amorphized around the periphery ofthe recess. A layer ofamorphous material having the same chemical composition as that ofthe initial substrate is deposited on the structure obtained. The structure obtained is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice ofthe initial substrate.

Abstract translation: 形成了在局部和表面上形成单晶格中的至少一个不连续性的初始单晶衬底1。 初始衬底在不连续处凹进。 单晶晶格围绕凹槽的周边非晶化。 在所获得的结构上沉积具有与初始底物相同的化学组成的无定形材料层。 对所获得的结构进行热退火，以使非晶材料重结晶，从而与初始衬底的单晶晶格连续。

公开(公告)号：US20020070757A1

公开(公告)日：2002-06-13

申请号：US09935292

申请日：2001-08-22

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: H03K019/0175

CPC classification number: G11C7/225 ,  G11C7/22 ,  H03K19/00361

Abstract: A buffer circuit includes an input for receiving a logic signal, and a transfer circuit for transferring the logic signal from the input to an output of the buffer circuit. The transfer circuit includes at least one logic gate having a trip point sensitive to a supply voltage of the buffer circuit. The buffer circuit further includes a delivery circuit for delivering an inhibit signal having a predetermined duration when the logic signal has a trailing edge and/or leading edge, and an inhibit circuit for inhibiting the transfer circuit and for isolating the output of the buffer circuit from the input of the buffer circuit when the inhibit signal is delivered. A storage circuit holds a logic value of the logic signal at the output of the buffer circuit when the inhibit signal is delivered.

Abstract translation: 缓冲电路包括用于接收逻辑信号的输入端和用于将逻辑信号从输入传送到缓冲电路的输出的传送电路。 传输电路包括至少一个具有对缓冲电路的电源电压敏感的跳变点的逻辑门。 缓冲电路还包括传送电路，用于在逻辑信号具有后沿和/或前沿时传送具有预定持续时间的禁止信号;以及禁止电路，用于禁止传输电路并将缓冲电路的输出与 当禁止信号被传送时缓冲电路的输入。 当禁止信号被传送时，存储电路保持在缓冲电路的输出处的逻辑信号的逻辑值。

公开(公告)号：US20020051091A1

公开(公告)日：2002-05-02

申请号：US09859731

申请日：2001-05-17

Applicant: STMicroelectronics S.A.

Inventor： Sebastien Dedieu ,  Frederic Paillardet ,  Isabelle Telliez

IPC: H04L027/20 ,  H04N005/38

CPC classification number: H03H11/22 ,  H03B27/00 ,  H03D7/125 ,  H03L7/0812 ,  H03L7/087

Abstract: At least a first base signal and a second base signal are mutually in quadrature and both are capable of mutually exhibiting a quadrature error. These signals are used to formulate two pairs of delayed signals that includes a first delayed signal that is delayed with respect to the first base signal, a second signal delayed in phase opposition with respect to the first delayed signal, a third signal delayed with respect to the second base signal, and a fourth delayed signal in phase opposition with respect to the third delayed signal. The value of each of the delays is continuously adjusted using two differential signals arising from a direct or an indirect cross-mixing of the two pairs of delayed signals to obtain the four delayed signals virtually in quadrature.

Abstract translation: 至少第一基本信号和第二基本信号相互正交，并且两者都能够相互呈现正交误差。 这些信号用于制定两对延迟信号，这两对延迟信号包括相对于第一基本信号延迟的第一延迟信号，相对于第一延迟信号相位相对延迟的第二信号，相对于第一延迟信号延迟的第三信号 第二基本信号和相对于第三延迟信号相位相反的第四延迟信号。 使用由两对延迟信号的直接或间接交叉混合产生的两个差分信号来连续地调整每个延迟的值，以获得虚拟地正交的四个延迟信号。

公开(公告)号：US20020024070A1

公开(公告)日：2002-02-28

申请号：US09895839

申请日：2001-06-29

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel

IPC: H01L029/80 ,  H01L031/112

CPC classification number: H03K17/693 ,  H03K17/102

Abstract: An integrated circuit receives as supply voltages a ground reference voltage, a logic supply voltage and a high voltage. A protection device is associated with at least one gate oxide circuit element. The protection device applies to a supply node of the circuit element either the logic supply voltage under normal conditions of operation of the integrated circuit, or the high voltage under abnormal conditions of operation of the integrated circuit for breaking down the gate oxide.

Abstract translation: 集成电路作为电源电压接收接地参考电压，逻辑电源电压和高电压。 保护装置与至少一个栅极氧化物电路元件相关联。 该保护装置在集成电路的正常工作状态下的逻辑电源电压或集成电路的异常运行状态下的高电压对电路元件的供电节点施加用于分解栅极氧化物。

公开(公告)号：US20020022333A1

公开(公告)日：2002-02-21

申请号：US09932513

申请日：2001-08-17

Applicant: STMicroelectronics S.A.

Inventor： Yves Morand ,  Jean-Luc Pelloie

IPC: H01L021/20 ,  H01L029/00

CPC classification number: H01L28/60 ,  H01L21/76895

Abstract: A production of a capacitor includes the simultaneous production, in at least part of an intertrack insulating layer (3) associated with a given metallization level, on the one hand, of the two electrodes (50, 70) and of the dielectric layer (60) of the capacitor and, on the other hand, of a conducting trench (41) which laterally extends the lower electrode of the capacitor, is electrically isolated from the upper electrode and has a transverse dimension smaller than the transverse dimension of the capacitor, and the production, in the interlevel insulating layer (8) covering the intertrack insulating layer, of two conducting pads (80, 81) which come into contact with the upper electrode of the capacitor and with the conducting trench, respectively.

Abstract translation: 电容器的生产包括在两个电极（50,70）和电介质层（60）中的至少一部分与给定的金属化水平相关联的交织绝缘层（3）的同时产生 ），另一方面，横向延伸电容器的下电极的导电沟槽（41）与上电极电隔离并且具有比电容器的横向尺寸小的横向尺寸，以及 在覆盖交织绝缘层的层间绝缘层（8）中分别与电容器的上电极和导电沟槽接触的两个导电焊盘（80,81）的制造。

公开(公告)号：US20020018330A1

公开(公告)日：2002-02-14

申请号：US09863811

申请日：2001-05-22

Applicant: STMicroelectronics S.A.

Inventor： Andre Bremond ,  Philippe Merceron

IPC: H02H005/04

CPC classification number: H02H5/042 ,  H02H5/044 ,  H02H9/042

Abstract: A series device for protection against a heating of aparallel protection element of an equipment of a telephone line, including a bi-directional cut-off element, of normally on state and placed in series with the parallel protection element, a temperature detection element, and a switching element adapted to turning off the cut-off element when the temperature detected by the detection element exceeds a predetermined threshold.

Abstract translation: 一种串联装置，用于防止正常导通状态并与并联保护元件串联放置的电话线设备的并联保护元件的加热装置，包括双向截止元件，温度检测元件和 当由检测元件检测到的温度超过预定阈值时，开关元件适于截断截止元件。