公开(公告)号：US07196372B1

公开(公告)日：2007-03-27

申请号：US10614177

申请日：2003-07-08

Applicant: Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

Inventor： Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

IPC: H01L29/788

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11568 ,  H01L29/785

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍，氧化物层，间隔物和一个或多个控制栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 氧化层形成在翅片上并用作存储器件的隧道氧化物。 间隔件邻近翅片的侧表面形成，并且控制栅极邻近间隔件形成。 间隔件用作非易失性存储器件的浮栅电极。

公开(公告)号：US07125776B2

公开(公告)日：2006-10-24

申请号：US11030191

申请日：2005-01-07

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/959

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

Abstract translation: 制造MOSFET型半导体器件的方法包括平坦化沉积在沟道上的栅极材料层。 平面化在包括初始“粗糙”平坦化然后是“精细”平坦化的多步骤过程中进行。 用于更精细平坦化的浆料可以包括倾向于粘附到栅极材料的低区域的添加材料。

公开(公告)号：US07091097B1

公开(公告)日：2006-08-15

申请号：US10933424

申请日：2004-09-03

Applicant: Eric N. Paton ,  Qi Xiang ,  Cyrus E. Tabery ,  Bin Yu ,  Robert B. Ogle

Inventor： Eric N. Paton ,  Qi Xiang ,  Cyrus E. Tabery ,  Bin Yu ,  Robert B. Ogle

IPC: H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-crystallizing portions of the deep amorphous regions to reduce their depth, and re-crystallizing the reduced amorphous regions to form activated final source/drain regions.

Abstract translation: 制造半导体器件的方法包括在衬底上形成栅电极并在衬底内形成深非晶区域。 并且注入掺杂剂以在深非晶区域的深度处形成深的源极/漏极区域，部分地重新结晶深非晶区域的部分以减小它们的深度，并且将还原的非晶区域再结晶以形成激活的最终光源 /漏区。

公开(公告)号：US07084018B1

公开(公告)日：2006-08-01

申请号：US10838228

申请日：2004-05-05

Applicant: Shibly S. Ahmed ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Bin Yu

IPC: H01L21/84

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing buried oxide undercut during FinFET formation includes forming a fin on a buried oxide layer and forming a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin. The method further includes forming a sacrificial oxide layer over the fin and source and drain regions and forming a gate over the fin, wherein the sacrificial oxide layer reduces undercutting of the buried oxide layer during gate formation.

Abstract translation: 在FinFET形成期间减少掩埋氧化物底切的方法包括在掩埋氧化物层上形成翅片并形成与鳍片的第一端相邻的源极区域和与鳍片的第二端部相邻的漏极区域。 该方法还包括在鳍片和源极和漏极区域上形成牺牲氧化物层并在鳍片上形成栅极，其中牺牲氧化物层在栅极形成期间减少掩埋氧化物层的底切。

公开(公告)号：US07041542B2

公开(公告)日：2006-05-09

申请号：US10754559

申请日：2004-01-12

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/338

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin. The method further includes forming a dummy gate over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the dummy gate to form a trench in the dielectric layer and forming a metal gate in the trench.

Abstract translation: 形成鳍状场效应晶体管的方法包括形成鳍片并形成与鳍片的第一端相邻的源极区域和与鳍片的第二端部相邻的漏极区域。 该方法还包括在鳍上方形成虚拟栅极，并在虚拟栅极周围形成电介质层。 该方法还包括去除伪栅极以在电介质层中形成沟槽并在沟槽中形成金属栅极。

公开(公告)号：US20050272105A1

公开(公告)日：2005-12-08

申请号：US10888530

申请日：2004-07-09

Applicant: Kalle Levon ,  Bin Yu ,  Yanxiu Zhou

Inventor： Kalle Levon ,  Bin Yu ,  Yanxiu Zhou

IPC: A61F13/15 ,  C12M1/34 ,  C12Q1/00 ,  G01N20060101 ,  G01N33/543 ,  G01N33/552 ,  G01N33/554 ,  G01N33/569

CPC classification number: C12Q1/00 ,  C07K9/00 ,  C07K14/32 ,  C07K17/00 ,  C12Q1/003 ,  G01N33/53 ,  G01N33/54353 ,  G01N33/5438 ,  G01N33/54393 ,  G01N33/552

Abstract: A real-time, portable peptide-containing potentiometric biosensor that can directly identify bacterial spores. Two peptides for specific recognition of B. subtilis and B. anthracis Sterne may be immobilized by a polysiloxane monolayer immobilization (PMI) technique. The sensors translate the biological recognition event into a potential change by detecting, for example, B. subtilis spores in a concentration range of 0.08-7.3×104 CFU/ml. The sensor exhibited highly selective recognition properties towards Bacillus subtilis spores over other kinds of spores. The selectivity coefficients of the sensors for other kinds of spores are in the range of 0-1.0×10−5. The biosensor system not only has the specificity to distinguish Bacillus subtilis spores in a mixture of B. subtilis and B. thuringiensis (thur.) Kurstaki spores, but also can discriminate between live and dead B. subtilis spores. Furthermore, the sensor can distinguish a Bacillus subtilis 1A700 from other B. subtilis strain. Assay time may be as low as about 5 minutes for a single test. Rapid identification of B. anthracis Sterne and B. anthracis ΔAmes was also provided.

Abstract translation: 一种可直接鉴定细菌孢子的实时便携式含肽电位生物传感器。 用于特异性识别枯草芽孢杆菌和炭疽芽孢杆菌的两种肽可以通过聚硅氧烷单层固定（PMI）技术来固定。 传感器通过检测例如浓度范围为0.08-7.3×10 4 CFU / ml的枯草芽孢杆菌孢子将生物识别事件转化为潜在的变化。 传感器表现出对枯草芽孢杆菌孢子与其他种类孢子的高选择性识别性能。 用于其他种类孢子的传感器的选择性系数在0-1.0×10 -5的范围内。 生物传感器系统不仅具有将枯草芽孢杆菌和苏云金芽孢杆菌（thur。）Kurstaki孢子的混合物中的枯草芽孢杆菌孢子区分开的特异性，而且可以区分活枯枯病芽孢杆菌孢子和活枯草芽孢杆菌孢子。 此外，传感器可以将枯草芽孢杆菌1A700与其他枯草芽孢杆菌菌株区分开来。 单次测试的测定时间可能低至约5分钟。 炭疽杆菌和炭疽杆菌的快速鉴定也提供了DeltaAmes。

公开(公告)号：US06967175B1

公开(公告)日：2005-11-22

申请号：US10726619

申请日：2003-12-04

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/302 ,  H01L21/336 ,  H01L21/461 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66818 ,  Y10S438/933

Abstract: A method of manufacturing a semiconductor device may include forming a fin on an insulator and forming a gate oxide on sides of the fin. The method may also include forming a gate structure over the fin and the gate oxide and forming a dielectric layer adjacent the gate structure. Material in the gate structure may be removed to define a gate recess. A width of a portion of the fin below the gate recess may be reduced, and a metal gate may be formed in the gate recess.

Abstract translation: 半导体器件的制造方法可以包括在绝缘体上形成翅片并在鳍的侧面形成栅极氧化物。 该方法还可以包括在鳍片和栅极氧化物上形成栅极结构，并形成与栅极结构相邻的电介质层。 可以去除栅极结构中的材料以限定栅极凹部。 可以减小栅极凹部下方的鳍的一部分的宽度，并且可以在栅极凹部中形成金属栅极。

公开(公告)号：US06960804B1

公开(公告)日：2005-11-01

申请号：US10633034

申请日：2003-10-10

Applicant: Chih-Yuh Yang ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Bin Yu

Inventor： Chih-Yuh Yang ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Bin Yu

IPC: H01L21/027 ,  H01L21/336 ,  H01L29/786 ,  H01L29/788

CPC classification number: H01L29/785 ,  H01L21/0276 ,  H01L29/42392 ,  H01L29/66795

Abstract: A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.

Abstract translation: 双半导体器件包括衬底，绝缘层，鳍和栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 翅片具有多个侧表面，顶表面和底表面。 栅极形成在绝缘层上并且围绕半导体器件的沟道区域中的鳍的顶表面，底表面和侧表面。 用门材料围绕翅片会导致总通道宽度增加和设备调整裕度更灵活。

公开(公告)号：US06921963B2

公开(公告)日：2005-07-26

申请号：US10830006

申请日：2004-04-23

Applicant: Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

Inventor： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

Abstract: A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.

Abstract translation: 这里描述了窄通道FinFET，其具有窄的通道宽度。 可以在窄通道上形成保护层，保护层比窄通道宽。

公开(公告)号：US20050153485A1

公开(公告)日：2005-07-14

申请号：US10754540

申请日：2004-01-12

Applicant: Shibly Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/335

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.

Abstract translation: 形成鳍状场效应晶体管的方法包括：在鳍片的第一端上形成翅片并形成源极区域，在鳍片的第二端部形成漏极区域。 该方法还包括在鳍上形成具有第一图案的第一半导体材料的虚拟栅极，并在虚拟栅极周围形成介电层。 该方法还包括去除第一半导体材料以在对应于第一图案的电介质层中留下沟槽，使在沟槽内暴露的鳍片的一部分变薄，并在沟槽内形成金属栅极。