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公开(公告)号:US20190378583A1
公开(公告)日:2019-12-12
申请号:US16205165
申请日:2018-11-29
Applicant: SanDisk Technologies LLC
Inventor: Yu-Chung Lien , Xiang Yang , Zhenming Zhou , Deepanshu Dutta , Huai-Yuan Tseng
Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
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公开(公告)号:US20190267096A1
公开(公告)日:2019-08-29
申请号:US15908239
申请日:2018-02-28
Applicant: SanDisk Technologies LLC
Inventor: Xiang Yang , Stanley Jeong , Wei Zhao , Huai-yuan Tseng , Deepanshu Dutta
Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. When the sense circuit is connected to the unselected bit line during the sense operation, the sense circuit is locked out in order to reduce current consumption. However, noise from the locked out sense circuit may be transmitted to the sense circuits connected to the selected bit lines through adjacent bit line coupling. In order to reduce the effect of the noise, charge transfer from the sense node may be blocked from passing to the unselected bit lines. Or, charge may be drained from the sense node, thereby preventing the charge from passing to the unselected bit lines.
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公开(公告)号:US20170178736A1
公开(公告)日:2017-06-22
申请号:US15385454
申请日:2016-12-20
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Xiang Yang , Huai-Yuan Tseng , Xiaochang Miao , Deepanshu Dutta
CPC classification number: G11C16/3427 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2211/5648
Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.
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