公开(公告)号：US5828124A

公开(公告)日：1998-10-27

申请号：US312472

申请日：1994-09-26

Applicant: Flavio Villa

Inventor： Flavio Villa

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/00 ,  H01L27/082 ,  H01L27/102

CPC classification number: H01L29/1004 ,  Y10S148/01

Abstract: A low-noise PNP transistor comprising a cutoff region laterally surrounding the emitter region in the surface portion of the transistor. The cutoff region has such a conductivity as to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. The cutoff region is formed by an N.sup.+ -type enriched base region arranged between the emitter region and the collector region.

Abstract translation: 一种低噪声PNP晶体管，包括横向围绕晶体管表面部分中的发射极区域的截止区域。 截止区域具有实际上关闭晶体管的表面部分的导电性，使得晶体管主要在主体部分中工作。 截止区域由布置在发射极区域和集电极区域之间的N +型富集基极区域形成。

公开(公告)号：US5821791A

公开(公告)日：1998-10-13

申请号：US730699

申请日：1996-10-11

Applicant: Maurizio Gaibotti ,  Francesco Adduci

Inventor： Maurizio Gaibotti ,  Francesco Adduci

IPC: H03K3/3562 ,  H03K3/289

CPC classification number: H03K3/35625

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths. Furthermore, a single clock signal is used to enable both master and slave sections. The ability to use a single clock signal without local regeneration coupled with minimizing the number of required components facilitates higher integrated circuit density and reduces power consumption.

Abstract translation: 公开并要求保护低功耗和高密度D触发器电路，特别是对于包括主器件部分和从器件部分的标准单元库。 主部分包括主锁存结构，将主锁存器结构连接到两个电源电压中的一个的主耦合电路，以及用于将数据应用于触发器的输入耦合电路。 从部分包括直接插入在两个电源电压之间的从锁存结构，以及将从锁存结构连接到主锁存结构的从耦合电路。 通过扩大输入耦合电路中的晶体管的源极面积，实现本发明的D触发器电路实现所需的晶体管的数量被最小化，这导致大的寄生电容并确保主锁存器的最佳操作。 此外，从锁存结构中的晶体管具有非最小栅极长度。 此外，单个时钟信号用于启用主和从部分。 使用无需本地再生的单个时钟信号与最小化所需组件数量的能力有助于实现更高的集成电路密度并降低功耗。

公开(公告)号：US5818775A

公开(公告)日：1998-10-06

申请号：US833901

申请日：1997-04-10

Applicant: Cosimo Torelli ,  Danilo Rimondi

Inventor： Cosimo Torelli ,  Danilo Rimondi

IPC: G11C8/08 ,  G11C11/418 ,  G11C13/00

CPC classification number: G11C8/08 ,  G11C11/418

Abstract: The invention relates to a memory comprising a matrix of memory cells; a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows of the matrix; a dummy bit line having an equivalent load as bit lines associated to columns of the matrix and which is discharged by a dummy memory cell when any row is selected; and circuitry for precharging the bit lines and the dummy bit line when no row is selected, and enabling said gates for transmission of the selection outputs of the row decoder in response to a clock signal. Each gate has an input coupled to the dummy bit line such that the gate is disabled as soon as the dummy bit line has discharged to a switching threshold of the gate.

Abstract translation: 本发明涉及包括存储器单元矩阵的存储器; 多个门，用于将行解码器的各个选择输出发送到矩阵的各行; 虚拟位线具有作为与矩阵的列相关联的位线的等效负载，并且当选择任何行时由虚拟存储器单元放电; 以及用于当没有行被选择时对位线和虚拟位线进行预充电的电路，以及响应于时钟信号使所述门用于传送行解码器的选择输出。 每个门具有耦合到虚拟位线的输入，使得一旦虚拟位线已经放电到门的切换阈值，门被禁止。

公开(公告)号：US5818760A

公开(公告)日：1998-10-06

申请号：US871226

申请日：1997-06-09

Applicant: Livio Baldi ,  Federico Pio

Inventor： Livio Baldi ,  Federico Pio

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC classification number: G11C16/30 ,  G11C16/12

Abstract: A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

公开(公告)号：US5818376A

公开(公告)日：1998-10-06

申请号：US798737

申请日：1997-02-13

Applicant: Marco Bianchessi ,  Sandro Dalle Feste ,  Nadia Serina

Inventor： Marco Bianchessi ,  Sandro Dalle Feste ,  Nadia Serina

IPC: H03M7/32 ,  H03M1/08 ,  H03M1/66 ,  H03M7/00

CPC classification number: H03M7/3008 ,  H03M7/3028 ,  H03M7/3042

Abstract: A method of injecting a whitening random signal in a Sigma Delta modulator with a high-pass transfer function of a quantization noise filter of a certain order, for converting a digital audio signal sampled at a certain clock frequency into an analog signal, comprises the steps of generating a flat-spectrum dither signal, filtering the dither signal with a high-pass transfer function of an order higher than the order of the transfer function of the Sigma Delta modulator, and summing the filtered signal to the sampled digital audio signal, quantized by the modulator. The method prevents the occurrence of disturbances that would otherwise occur as a result of intermodulation of subtle colorations observable in the vicinity of the Nyquist frequency. The disclosed hardware implementation of the method adds little to the hardware complexity.

Abstract translation: 一种在具有一定次序的量化噪声滤波器的高通传递函数的Sigma Delta调制器中注入白化随机信号的方法，用于将以某一时钟频率采样的数字音频信号转换为模拟信号，包括步骤 产生平坦频抖动信号，以高于Sigma Delta调制器的传递函数的阶数的高通传递函数对抖动信号进行滤波，并将经滤波的信号与采样的数字音频信号相加，量化 通过调制器。 该方法防止了由于在奈奎斯特频率附近可观察到的微妙着色而导致的干扰的发生。 所公开的该方法的硬件实现对硬件复杂性几乎没有增加。

公开(公告)号：US5817557A

公开(公告)日：1998-10-06

申请号：US792893

申请日：1997-01-31

Applicant: Livio Baldi

Inventor： Livio Baldi

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L29/66825 ,  Y10S438/981

Abstract: A process including the steps of forming a gate oxide layer on a semiconductor substrate; masking the gate oxide layer with a nitride mask forming openings in the gate oxide layer using the nitride mask; and forming, at the openings, tunnel oxide regions of a thickness smaller than the thickness of the gate oxide layer. The nitride mask presents a thickness smaller than the width of the openings to improve etching of the gate oxide layer and subsequent washing. The mask also protects the covered layers when etching the gate oxide and growing the tunnel oxide regions, and is removed easily without damaging the exposed layers.

Abstract translation: 一种方法，包括在半导体衬底上形成栅极氧化层的步骤; 使用氮化物掩模，用栅极氧化物层中的氮化物掩模掩蔽栅极氧化物层; 并且在所述开口处形成厚度小于所述栅极氧化物层的厚度的隧道氧化物区域。 氮化物掩模的厚度小于开口的宽度，以改善栅极氧化物层的蚀刻和随后的洗涤。 当蚀刻栅极氧化物并生长隧道氧化物区域时，掩模还保护被覆层，并且容易地去除而不损坏暴露的层。

公开(公告)号：US5808477A

公开(公告)日：1998-09-15

申请号：US657878

申请日：1996-05-31

Applicant: Alberto Gola ,  Giona Fucili ,  Marcello Leone ,  Patrizia Milazzo

Inventor： Alberto Gola ,  Giona Fucili ,  Marcello Leone ,  Patrizia Milazzo

IPC: H03K17/082 ,  H03K19/003 ,  H03K19/08

CPC classification number: H03K17/082 ,  H03K19/00315

Abstract: A sense and protection circuit against short circuits for digital outputs, comprising a logic gating circuit of the exclusive OR type (EX1) which has a first input terminal connected to a signal input node (IN) and an output terminal which is connected to an input terminal of a signal level shifter output stage (B). A second logic gating circuit of the exclusive OR type (EX2) has a first input terminal connected to the input node (IN) and a second input terminal connected, through an inverting circuit (IN1), to an output terminal (OUT) of the output stage (B). A second input terminal of the first logic gate circuit is coupled to an output terminal of the second logic gate circuit through a comparator circuit (SCH1) and a delay circuit means (C,R,D).

Abstract translation: 一种用于数字输出的短路的感测和保护电路，包括具有连接到信号输入节点（IN）的第一输入端和异步OR类型（EX1）的逻辑门控电路，输出端连接到输入端 信号电平移位器输出级（B）的端子。 异或类型（EX2）的第二逻辑门控电路具有连接到输入节点（IN）的第一输入端和通过反相电路（IN1）连接到输入端（IN）的输出端（OUT）的第二输入端 输出级（B）。 第一逻辑门电路的第二输入端通过比较器电路（SCH1）和延迟电路装置（C，R，D）耦合到第二逻辑门电路的输出端。

公开(公告)号：US5805500A

公开(公告)日：1998-09-08

申请号：US877921

申请日：1997-06-18

Applicant: Giovanni Campardo ,  Rino Micheloni ,  Marco Maccarrone

Inventor： Giovanni Campardo ,  Rino Micheloni ,  Marco Maccarrone

IPC: G11C16/28 ,  G11C16/06

CPC classification number: G11C16/28

Abstract: The current flowing through a cell to be read, forming part of a nonvolatile memory array and presenting a characteristic with a predetermined slope, is amplified N times and compared with a reference current presenting a two portion characteristic: a first portion extending between a predetermined threshold value and a trigger value, and presenting a slope equal to that of the memory cell characteristic, and a second portion extending from the trigger value, and presenting a slope amplified N times with respect to that of the cell characteristic and therefore equal to the amplified slope of the cell.

Abstract translation: 流过待读取的单元的电流，形成非易失性存储器阵列的一部分并呈现具有预定斜率的特性，被放大N倍，并与呈现两部分特性的参考电流进行比较：在预定阈值之间延伸的第一部分 值和触发值，并且呈现与存储器单元特性相同的斜率，以及从触发值延伸的第二部分，并且呈现相对于单元特性的N倍的斜率，因此等于放大的 细胞斜率

公开(公告)号：US5796275A

公开(公告)日：1998-08-18

申请号：US791700

申请日：1997-01-30

Applicant: Paolo Rolandi ,  Massimo Montanaro

Inventor： Paolo Rolandi ,  Massimo Montanaro

IPC: G01R19/165 ,  H03K17/30 ,  H03K5/153

CPC classification number: H03K17/302 ,  G01R19/16519

Abstract: The circuit, in accordance with the present invention is for detecting the presence at a signal input of a high voltage higher than a predetermined value and signaling it to a signal output through a logical type signal. The circuit comprises one or more first transistors of MOS type and of a predetermined conductivity type, each being diode-connected and having its body terminal connected to the source terminal, and having principal conduction paths connected in series for current conduction between a first node and a ground input. The circuit also includes two or more second transistors of the MOS type and of the same conductivity type, with each one being diode-connected and having its body terminal connected to the source terminal and having principal conduction paths connected in series for current conduction between the signal input and the first node. At least one first logical inverter of the CMOS type has its input connected to the first node and its output coupled to the signal output and is also connected for power supply to a power supply input and to the ground input.

Abstract translation: 根据本发明的电路用于检测在高于预定值的高电压的信号输入处的存在并将其信号通过逻辑类型信号输出的信号。 电路包括一个或多个MOS型和预定导电类型的第一晶体管，每个第二晶体管是二极管连接的，其主体端子连接到源极端子，并且具有串联连接的主要导电路径，用于在第一节点和 地面输入。 该电路还包括两个或更多个MOS型和相同导电类型的第二晶体管，其中每一个二极管连接并且其主体端子连接到源极端子并且具有串联连接的主要导电路径，用于在 信号输入和第一个节点。 CMOS型的至少一个第一逻辑逆变器的输入连接到第一节点，其输出耦合到信号输出，并且还被连接用于电源输入和接地输入。

公开(公告)号：US5793086A

公开(公告)日：1998-08-11

申请号：US772301

申请日：1996-12-23

Applicant: Emilio Giambattista Ghio ,  Giuseppe Meroni ,  Danilo Re ,  Livio Baldi

Inventor： Emilio Giambattista Ghio ,  Giuseppe Meroni ,  Danilo Re ,  Livio Baldi

IPC: G11C17/12 ,  H01L21/8238 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/112 ,  H01L29/78

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract translation: 在具有LDD单元的MOS或CMOS技术中制造的ROM存储器可以通过将已经形成的漏极区域与细胞的沟道区域去耦合而被有利地编程在相对较先进的制造阶段中，以通过将量子点 足以颠倒与沟道区相邻的漏极区的一部分中的导电性。 在CMOS工艺中，编程掩模可以是通常用于注入某种导电性晶体管的源极/漏极区域的特意修改的掩模。 通过使用高能量注入和专用掩模，编程可以在制造过程的甚至后期进行。