公开(公告)号：US09140975B2

公开(公告)日：2015-09-22

申请号：US14106219

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Chanro Park ,  Wenhui Wang ,  Hui Zang

IPC: G03F1/62 ,  G03F1/64 ,  G03F1/00 ,  G03F1/22

CPC classification number: G03F1/142 ,  G03F1/22 ,  G03F1/62 ,  G03F1/64

Abstract: A method of forming an improved EUV mask and pellicle with airflow between the area enclosed by the mask and pellicle and the area outside the mask and pellicle and the resulting device are disclosed. Embodiments include forming a frame around a patterned area on an EUV mask; forming a membrane over the frame; and forming holes in the frame.

Abstract translation: 公开了一种在由掩模和防护薄膜组成的区域与掩模和防护薄膜之间的区域以及所得到的装置之间形成改进的EUV掩模和防护薄膜组件的方法。 实施例包括在EUV掩模上的图案化区域周围形成框架; 在框架上形成膜; 并在框架中形成孔。

公开(公告)号：US20150140698A1

公开(公告)日：2015-05-21

申请号：US14607161

申请日：2015-01-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L21/66 ,  H01L21/8234

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

公开(公告)号：US20150140697A1

公开(公告)日：2015-05-21

申请号：US14607160

申请日：2015-01-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L21/66 ,  H01L21/8234

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

Abstract translation: 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括在MPLP的第一步骤期间形成具有第一和第二栅极区的测试宏的有源区，以及在MPLP的第二步骤期间在有源区中形成第一和第二源/漏区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点和确定 如果通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路，在MPLP的步骤的第一步骤和第二步骤之间发生覆盖移位。

公开(公告)号：US10998422B2

公开(公告)日：2021-05-04

申请号：US16730712

申请日：2019-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L21/70 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8238

Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.

公开(公告)号：US10896853B2

公开(公告)日：2021-01-19

申请号：US16396775

申请日：2019-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Rinus Tek Po Lee ,  Wei Hong ,  Hui Zang ,  Hong Yu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/306

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages. The present disclosure further provides a method of forming structures in a semiconductor device by forming a first and second cavities having sidewalls and bottom surfaces in a dielectric structure, where the first cavity has a narrower opening than the second cavity, forming a first material layer in the first and second cavities, forming a protective layer over the first material layer, where the protective layer fills the first cavity and conformally covers the sidewall and the bottom surfaces of the second cavity, performing a first isotropic etch on the protective layer to selectively remove a portion of the protective layer and form a retained portion of the protective layer, performing a second isotropic etch on the first material layer to selectively remove a portion of the first material layer and form a retained portion of the first material layer, removing the retained portion of the protective layer, and forming a second material layer in the first and second cavities, the second material layer being formed on the retained portion of the first material layer.

公开(公告)号：US10892338B2

公开(公告)日：2021-01-12

申请号：US16169269

申请日：2018-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

公开(公告)号：US10825741B2

公开(公告)日：2020-11-03

申请号：US16196413

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/092

Abstract: One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.

公开(公告)号：US10818498B1

公开(公告)日：2020-10-27

申请号：US16407744

申请日：2019-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Hui Zang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L29/417 ,  H01L21/768

Abstract: Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US10797046B1

公开(公告)日：2020-10-06

申请号：US16369788

申请日：2019-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L27/07 ,  H01L49/02 ,  H01L29/78 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L27/088 ,  H01L27/02 ,  H01L27/06

Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material.

公开(公告)号：US20200303261A1

公开(公告)日：2020-09-24

申请号：US16360183

申请日：2019-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Jiehui Shu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423

Abstract: A method of forming an IC structure includes providing a metal gate structure, a spacer adjacent the metal gate structure and a contact to each of a pair of source/drain regions adjacent sides of the spacer. The spacer includes a first dielectric having a first dielectric constant. The metal gate structure is recessed, and the spacer is recessed to have an upper surface of the first dielectric below an upper surface of the metal gate structure, leaving a lower spacer portion. An upper spacer portion of a second dielectric having a dielectric constant lower than the first dielectric is formed over the lower spacer portion. A gate cap is formed over the metal gate structure and the upper spacer portion. The second dielectric can include, for example, an oxide or a gas. The method may reduce effective capacitance and gate height loss, and improve gate-to-contact short margin.