公开(公告)号：US07314809B2

公开(公告)日：2008-01-01

申请号：US11076908

申请日：2005-03-11

Applicant: Wen-Pin Chiu

Inventor： Wen-Pin Chiu

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: A method for forming a shallow trench isolation (STI) structure with reduced stress is described. An amorphous silicon layer is deposited on a trench surface of a shallow trench isolation structure, and the amorphous silicon is then oxidized by thermal oxidation to form a liner oxide. The thickness of the liner oxide is uniform to reduce stress caused by a liner oxide having non-uniform thickness in the prior art, and the leakage risk between the semiconductor devices can thus be prevented.

Abstract translation: 描述了一种形成具有减小应力的浅沟槽隔离（STI）结构的方法。 非晶硅层沉积在浅沟槽隔离结构的沟槽表面上，然后通过热氧化氧化非晶硅以形成衬里氧化物。 衬垫氧化物的厚度是均匀的，以减少由现有技术中具有不均匀厚度的衬垫氧化物引起的应力，因此可以防止半导体器件之间的泄漏风险。

公开(公告)号：US20070290185A1

公开(公告)日：2007-12-20

申请号：US11525286

申请日：2006-09-22

Applicant: Wen-Han Wang

Inventor： Wen-Han Wang

IPC: H01L29/04

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

Abstract: Phase change memory cells and methods for fabricating the same are provided. In an exemplary embodiment, a phase change memory cell comprises a first electrode disposed over a substrate along a first direction. A first dielectric layer is formed over the first electrode. A conductive contact is formed in the first dielectric layer, electrically contacting the first electrode, wherein the conductive contact has an L-shaped or reverse L-shaped () cross section. A second dielectric layer is formed over the first dielectric layer. A phase change layer is partially formed over the first and the second dielectric layers, electrically contacting the conductive contact. A third dielectric layer is formed over the phase change layer and the first and second dielectric layers with an opening therein. A second electrode layer is formed over the third dielectric layer and fills the opening to electrically contact the phase change layer.

Abstract translation: 提供了相变存储单元及其制造方法。 在示例性实施例中，相变存储单元包括沿着第一方向设置在衬底上的第一电极。 第一电介质层形成在第一电极上。 导电接触形成在第一电介质层中，与第一电极电接触，其中导电接触具有L形或反向L形（）横截面。 在第一电介质层上形成第二电介质层。 相变层部分地形成在第一和第二介电层上，与导电接触电接触。 第三电介质层形成在相变层上，第一和第二电介质层在其中具有开口。 在第三电介质层上形成第二电极层，并填充开口以与相变层电接触。

公开(公告)号：US07298669B2

公开(公告)日：2007-11-20

申请号：US11456891

申请日：2006-07-12

Applicant: Jon Allan Faue

Inventor： Jon Allan Faue

IPC: G11C8/18

CPC classification number: G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A clock generator is provided that is compatible with both DDR1 and DDR2 applications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A circuit block within the clock generator detects when a read or write is active and initiates a YCLK signal on the next falling edge of the internal clock. Two separate mechanisms are used for determining when to terminate the YCLK. One mechanism is a timer path and the other is a path determined by DDR1 and DDR2 control signals. The timer path is strictly time based and is the same for DDR1 and DDR2 parts or modes of operation. The other signal path is different for DDR1 and DDR2 operating modes. A DDR1 control signal turns off YCLK at the next rising edge of the internal clock, and a DDR2 control signal turns off YCLK at the next falling edge of the internal clock.

Abstract translation: 提供与DDR1和DDR2应用兼容的时钟发生器。 即使主芯片时钟始终运行，内部YCLK信号仅在集成电路存储器上发生有效读取或写入时导通。 时钟发生器内的一个电路块检测读或写何时有效，并在内部时钟的下一个下降沿启动YCLK信号。 使用两个单独的机制来确定何时终止YCLK。 一种机制是定时器路径，另一种是由DDR1和DDR2控制信号确定的路径。 定时器路径是基于时间的，对于DDR1和DDR2部件或操作模式是相同的。 DDR1和DDR2操作模式的其他信号路径不同。 DDR1控制信号在内部时钟的下一个上升沿关闭YCLK，DDR2控制信号在内部时钟的下一个下降沿关闭YCLK。

公开(公告)号：US20070224767A1

公开(公告)日：2007-09-27

申请号：US11456381

申请日：2006-07-10

Applicant: Jim Lin ,  San-Jung Chang ,  Yu-Cheng Lo

Inventor： Jim Lin ,  San-Jung Chang ,  Yu-Cheng Lo

IPC: H01L21/336

CPC classification number: H01L29/42376 ,  H01L21/28238 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7834

Abstract: A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and extends above the substrate. The gate further comprises a polysilicon layer and a conductive layer; wherein the polysilicon layer is formed inside the recessed trench of the substrate, and the conductive layer is formed above the polysilicon layer and extends above the substrate. Moreover, the width of the conductive layer increases gradually bottom-up. The source and the drain are formed respectively at two sides of the gate. The reverse spacer is formed above the polysilicon layer and against the sidewall of the conductive layer.

Abstract translation: 提供具有凹槽的半导体器件及其制造方法。 半导体器件包括衬底，栅极，源极，漏极和反向间隔物。 衬底包括凹槽。 栅极形成在凹槽的上方并在衬底上延伸。 栅极还包括多晶硅层和导电层; 其中所述多晶硅层形成在所述衬底的所述凹槽内，并且所述导电层形成在所述多晶硅层上方并在所述衬底上方延伸。 此外，导电层的宽度自底向上增加。 源极和漏极分别形成在栅极的两侧。 反向间隔物形成在多晶硅层上方并抵靠导电层的侧壁上。

公开(公告)号：US20070215989A1

公开(公告)日：2007-09-20

申请号：US11376319

申请日：2006-03-16

Applicant: Mu Tsai ,  Li Chen

Inventor： Mu Tsai ,  Li Chen

IPC: H01L23/495

CPC classification number: H01L23/49541 ,  H01L23/4951 ,  H01L23/4952 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor chip assembly comprises a semiconductor chip including a first contact and a second contact positioned at a first side of the first contact, a first lead including an inner end, a second lead including a body positioned at a second side of the first lead and an inner segment positioned between the contacts of semiconductor chip and the inner end of the first lead, a first bonding wire connecting the first contact to the inner end of the first lead and a second bonding wire connecting the second contact and the inner segment of the second lead. The first side of the first contact is in the opposite direction to the second side of the first lead, and the first bonding wire and the second bonding wire do not cross each other. Preferably, the second lead further includes a middle portion between the body and the inner segment, or the second lead is L-shaped.

Abstract translation: 半导体芯片组件包括半导体芯片，其包括第一触点和位于第一触点的第一侧的第二触点，第一引线，包括内端，第二引线包括位于第一引线的第二侧的主体， 位于半导体芯片的触点和第一引线的内端之间的内部段，将第一触点连接到第一引线的内端的第一接合线和连接第二触点和第二触点的内部段的第二接合线 第二个领先。 第一接触的第一侧与第一引线的第二侧相反，第一接合线和第二接合线不交叉。 优选地，第二引线还包括主体和内部段之间的中间部分，或者第二引线为L形。

公开(公告)号：US20070213862A1

公开(公告)日：2007-09-13

申请号：US11433448

申请日：2006-05-15

Applicant: Hong Chang ,  Jui Hu ,  Hung Chiou

Inventor： Hong Chang ,  Jui Hu ,  Hung Chiou

IPC: G06F19/00

CPC classification number: G05B19/4183 ,  G05B2219/31244 ,  G05B2219/45031 ,  Y02P90/10 ,  Y02P90/14

Abstract: A data collector control system for semiconductor manufacturing comprises a data collector and a automatic communication port switch control circuit. The control system is placed between an equipment and an equipment automation programming (EAP) system. The data collector processes and transmits communication messages between the equipment and the EAP system while the data collector operates normally. The communication messages between the equipment and the EAP system are transmitted through the control circuit instead of the data collector while the data collector operates abnormally.

Abstract translation: 用于半导体制造的数据采集器控制系统包括数据采集器和自动通信端口开关控制电路。 控制系统位于设备和设备自动化程序设计（EAP）系统之间。 数据采集​​器在数据采集器正常工作的同时处理和传输设备与EAP系统之间的通信消息。 设备和EAP系统之间的通信信息通过控制电路而不是数据采集器传输，而数据采集器工作异常。

公开(公告)号：US07262093B2

公开(公告)日：2007-08-28

申请号：US10891076

申请日：2004-07-15

Applicant: Tings Wang

Inventor： Tings Wang

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

Abstract: A flash memory cell is provided. The flash memory cell includes a substrate having a source and a drain formed therein, a bit line contact formed above the drain, a control gate formed above the substrate, a spacer floating gate formed above the substrate and adjacent to the control gate, and a first spacer formed between the bit line contact and the control gate, wherein the first spacer is in contact with both the bit line contact and the control gate.

Abstract translation: 提供闪存单元。 闪存单元包括其上形成有源极和漏极的衬底，形成在漏极上方的位线接触件，形成在衬底上方的控制栅极，形成在衬底上并与控制栅极相邻的间隔物浮动栅极，以及 第一间隔件形成在位线接触件和控制栅极之间，其中第一间隔件与位线接触件和控制栅极接触。

公开(公告)号：US07251172B2

公开(公告)日：2007-07-31

申请号：US11071852

申请日：2005-03-03

Applicant: Jon Allan Faue ,  Craig Barnett

Inventor： Jon Allan Faue ,  Craig Barnett

IPC: G11C8/00 ,  G11C7/00 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C8/18

Abstract: An additive latency circuit for a DDR2 standard compliant integrated circuit memory includes a half flip-flop register assigned for each case of additive latency. A unique clock is generated to control each bit in the register chain. Sufficient register bits are required in the chain to support the highest additive latency specified. For latency settings less than the maximum, those clocks assigned to the bits above the chosen latency are enabled so the data passes through un-clocked. For the additive latency zero case, a separate bypass path is provided. Both address and command information is delayed by the additive latency delay chain. Once delayed by the proper number of cycles, the address information remains in that state until the time when a new state is required. Command information remains valid for one cycle upon reaching the proper delay point. A reset circuit is provided to reset command signals.

Abstract translation: 用于DDR2标准兼容集成电路存储器的附加延迟电路包括为每种附加延迟情况分配的半触发器寄存器。 产生唯一的时钟来控制寄存器链中的每个位。 链中需要足够的寄存器位来支持指定的最高附加延迟。 对于小于最大值的延迟设置，分配给所选等待时间以上的位的时钟将被启用，以便数据通过非时钟。 对于附加延迟零情况，提供单独的旁路路径。 地址和命令信息都被加法延迟延迟链延迟。 一旦延迟了适当的周期数，地址信息将保持在该状态，直到需要新状态为止。 命令信息在达到适当的延迟点后保持有效。 提供复位电路以复位指令信号。

公开(公告)号：US20070170090A1

公开(公告)日：2007-07-26

申请号：US11401835

申请日：2006-04-12

Applicant: Ya Po ,  Ting Wang

Inventor： Ya Po ,  Ting Wang

IPC: B65D85/00 ,  B65D81/24 ,  B65D90/22

CPC classification number: H01L21/67393 ,  H01L21/67017

Abstract: A wafer-transferring pod capable of monitoring process environment comprises a body and a sampling mechanism positioned on a top surface, a back surface or one of two side surfaces of the body for adsorbing contamination. The sampling mechanism comprises an inner chamber filled with adsorbent such as glass wool and a plurality of openings positioned on sidewalls of the inner chamber. In addition, the sampling mechanism may comprise a movable door and an opening for a user to absorb the air from the body without opening a front cover of the wafer-transferring pod. Further, the sampling mechanism may comprise an inner member positioned on the body and an outer member buckled into the inner member, wherein the inner member and the outer member have an opening through which the user can absorb the air in the body without opening the front cover of the wafer-transferring pod.

Abstract translation: 能够监测处理环境的晶片转移容器包括位于主体的顶表面，后表面或两个侧表面之一中的吸收污染的主体和取样机构。 采样机构包括填充有诸如玻璃棉的吸附剂的内室和位于内室的侧壁上的多个开口。 此外，采样机构可以包括可移动门和用于使用者从主体吸收空气的开口，而不打开晶片传送盒的前盖。 此外，采样机构可以包括定位在主体上的内部构件和外部构件弯曲到内部构件中，其中内部构件和外部构件具有开口，用户可以通过该开口吸收身体中的空气而不打开前部 晶片转移盒的盖子。

公开(公告)号：US20070155187A1

公开(公告)日：2007-07-05

申请号：US11387888

申请日：2006-03-24

Applicant: Chung Chen ,  Chih Chu ,  Jih Chou

Inventor： Chung Chen ,  Chih Chu ,  Jih Chou

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/7621 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/76213

Abstract: A method for preparing a gate oxide layer is described. First, a trench surrounding an active area is formed in a substrate, and a dielectric block is then formed in the trench such that an upper surface of the dielectric block is not aligned with that of the substrate. Subsequently, an ion implantation process is performed to implant nitrogen-containing dopants into the substrate in the active area, and a thermal oxidation process is then performed to form a gate oxide layer on the surface of the substrate in the active area. Particularly, the concentration of the nitrogen-containing dopants at the center of the active area is higher than that at the edge of the active area. The nitrogen-containing dopants inhibit the reaction rate of the thermal oxidation process, so as to prevent the gate oxide layer from thinning at the edge near the trench.

Abstract translation: 描述了制备栅氧化层的方法。 首先，在基板中形成围绕有源区的沟槽，然后在沟槽中形成介质块，使得介质块的上表面与衬底的上表面不一致。 随后，进行离子注入工艺以将含氮掺杂剂注入到有源区域中的衬底中，然后执行热氧化工艺以在有源区域中在衬底的表面上形成栅极氧化层。 特别地，有源区中心的含氮掺杂剂的浓度高于有源区的边缘处的浓度。 含氮掺杂剂抑制热氧化过程的反应速率，以防止栅极氧化层在沟槽附近的边缘变薄。