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231.发明授权Integrated circuit comprising a MOS transistor having a sigmoid response and corresponding method of fabrication 有权包括具有S形反应的MOS晶体管和相应的制造方法的集成电路公开(公告)号：US09368611B2
公开(公告)日：2016-06-14
申请号：US13853111
申请日：2013-03-29
Inventor： Philippe Galy , Patrice Dehan , Boris Heitz , Jean Jimenez
IPC: H01L29/66 , H01L29/78 , H01L29/417 , H01L27/07
CPC classification number: H01L29/78 , H01L27/0727 , H01L29/41775 , H01L29/66553 , H01L29/66628 , H01L29/66643 , H01L29/7839
Abstract: An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.
Abstract translation: 集成电路可以包括具有S形响应的至少一个MOS晶体管。 至少一个MOS晶体管可以包括栅极区域的任一侧上的衬底，源极区域，漏极区域，栅极区域和绝缘间隔区域。 衬底可以包括位于绝缘间隔区之间的栅极区域下方的第一区域。 源极和漏极区域中的至少一个可以通过位于绝缘间隔区域下方的衬底的第二区域与衬底的第一区域分离，绝缘间隔区域可以具有与衬底的第一区域相同类型的导电性。
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公开(公告)号：US09299668B2
公开(公告)日：2016-03-29
申请号：US13705503
申请日：2012-12-05
Applicant: STMicroelectronics S.A.
Inventor： Johan Bourgeat , Philippe Galy
CPC classification number: H01L23/60 , H01L27/0262 , H01L27/0274 , H01L27/0296 , H01L29/0692 , H01L29/747 , H01L2924/0002 , H02H9/04 , H01L2924/00
Abstract: A device for protecting a set of N nodes from electrostatic discharges, wherein N is greater than or equal to three, includes a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal. Each unit includes at least one MOS transistor including a parasitic transistor connected between a pair of the N nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.
Abstract translation: 用于保护一组N个节点免受静电放电的装置，其中N大于或等于3，包括分别具有分别连接到N个节点的N个第一终端的N个单元的集合和连接在一起的N个第二终端以形成公共 终奌站。 每个单元包括至少一个MOS晶体管，其包括连接在一对N个节点之间的寄生晶体管，并且在所述一对节点之间存在电流脉冲的情况下，配置为至少临时地以包括MOS- 在亚阈值模式下工作和双极晶体管的工作。
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公开(公告)号：US09236407B2
公开(公告)日：2016-01-12
申请号：US14144168
申请日：2013-12-30
Inventor： François Roy , Yvon Cazaux
IPC: H01L27/146
CPC classification number: H01L27/14603 , H01L27/14614 , H01L27/1463 , H01L27/14656
Abstract: An image sensor arranged inside and on top of a semiconductor substrate, having a plurality of pixels, each including: a photosensitive area, a read area, and a storage area extending between the photosensitive area and the read area; at least one first insulated vertical electrode extending in the substrate between the photosensitive area and the storage area; and at least one second insulated vertical electrode extending in the substrate between the storage area and the read area.
Abstract translation: 布置在半导体衬底的内部和顶部的具有多个像素的图像传感器，每个像素包括：感光区域，读取区域和在感光区域和读取区域之间延伸的存储区域; 至少一个第一绝缘垂直电极，其在所述基板中在所述光敏区域和所述存储区域之间延伸; 以及在所述存储区域和所述读取区域之间的所述衬底中延伸的至少一个第二绝缘垂直电极。
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公开(公告)号：US20160005836A1
公开(公告)日：2016-01-07
申请号：US14853719
申请日：2015-09-14
Applicant: STMicroelectronics S.A.
Inventor： Pascal CHEVALIER , Didier CELI , Jean-Pierre BLANC , Alain CHANTRE
CPC classification number: H01L29/66242 , H01L21/8249 , H01L27/0623 , H01L29/66325 , H01L29/737 , H01L29/7378
Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.
Abstract translation: 本公开涉及一种方法，其包括在第一和第二隔离沟槽之间的第一区域中暴露硅衬底的表面，在第一区域中蚀刻硅衬底以在第一和第二隔离沟槽之间形成凹陷，以及形成 通过在凹部中包含SiGe的膜的选择性外延生长，异质结双极晶体管的基极。
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公开(公告)号：US09077282B2
公开(公告)日：2015-07-07
申请号：US13745634
申请日：2013-01-18
Inventor： Yvan Morandini , Romain Debrouke
CPC classification number: H03B28/00 , H03B5/12 , H03B5/1212 , H03B5/1228 , H03B5/1253 , H03B5/1265 , H03H11/00 , H03J3/20
Abstract: A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal.
Abstract translation: 一种可变电容器件，包括：第一和第二晶体管，其由器件的第一和第二节点之间的主要电流节点串联连接，第一晶体管的控制节点适于接收第一控制信号，第二晶体管的控制节点 晶体管适于接收第二控制信号; 以及适于从选择信号产生第一和第二控制信号的控制电路。
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Patent Agency Ranking
公开(公告)号：US09052560B2
公开(公告)日：2015-06-09
申请号：US13920206
申请日：2013-06-18
Inventor： Michel Marty , Flavien Hirigoyen , Josep Segura Puchades , Hélène Wehbe-Alause , Umberto Rossini
IPC: H01L33/36 , G02F1/1368 , G02F1/1362
CPC classification number: G02F1/1368 , G02F1/136209 , G02F1/136213 , G02F1/136277 , G02F2001/136281 , H01L33/36
Abstract: A nanoprojector panel formed of an array of cells, each cell including a liquid crystal layer between upper and lower transparent electrodes, a MOS control transistor being arranged above the upper electrode, each transistor being covered with at least three metallization levels. The transistor of each cell extends in a corner of the cell so that the transistors of an assembly of four adjacent cells are arranged in a central region of the assembly. The upper metallization level extends above the transistors of each the assembly of four adjacent cells. The panel includes, for each assembly of four adjacent cells, a first conductive ring surrounding the transistors, the first ring extending from the lower metallization level to the upper electrode of each cell, with an interposed insulating material.
Abstract translation: 一种由单元阵列形成的纳米光电板面板，每个单元包括上透明电极和下透明电极之间的液晶层，MOS控制晶体管布置在上电极上方，每个晶体管被覆盖有至少三个金属化水平。 每个单元的晶体管延伸在单元的角部，使得四个相邻单元的组件的晶体管被布置在组件的中心区域中。 上部金属化水平延伸到四个相邻单元的每个组件的晶体管之上。 对于四个相邻电池的每个组件，面板包括围绕晶体管的第一导电环，第一环从下部金属化层延伸到每个电池的上部电极，并具有插入的绝缘材料。
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公开(公告)号：US08981529B2
公开(公告)日：2015-03-17
申请号：US13745613
申请日：2013-01-18
Inventor： Yvan Morandini , Romain Debrouke
CPC classification number: H01L29/93 , H01L29/66174 , H03B1/00 , H03B5/1212 , H03B5/1253 , H03J3/20 , H03J2200/10
Abstract: A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.
Abstract translation: 一种可变电容装置，包括：第一和第二晶体管并联耦合在电容性装置的第一和第二节点之间，第一晶体管的控制节点适于接收控制信号，第二晶体管的控制节点适于接收 控制信号的反相，其中第一和第二晶体管形成在相同的半导体阱中。
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公开(公告)号：US08907284B2
公开(公告)日：2014-12-09
申请号：US13692691
申请日：2012-12-03
Applicant: STMicroelectronics S.A.
Inventor： Hani Sherry , Andreia Cathelin , Ullrich Pfeiffer , Janusz Grzyb , Richard Al Hadi
CPC classification number: G01J5/34 , G05F3/26 , H01Q1/2283 , H01Q7/00 , H03K3/0315
Abstract: A pixel circuit may include a detection circuit having first and second transistors coupled in series between differential output nodes of an antenna. The antenna may be configured to be sensitive to terahertz radiation. The pixel circuit may also include a capacitor coupled to an intermediate node between the first and second transistors, and control circuitry coupled to control nodes of the first and second transistors. The control circuitry may be configured for selectively applying to the control nodes a gate biasing voltage for biasing the control nodes of the first and second transistors during a detection phase of the pixel circuit, and/or a reset voltage for resetting a voltage stored by the capacitor.
Abstract translation: 像素电路可以包括具有串联耦合在天线的差分输出节点之间的第一和第二晶体管的检测电路。 天线可以被配置为对太赫兹辐射敏感。 像素电路还可以包括耦合到第一和第二晶体管之间的中间节点的电容器，以及耦合到第一和第二晶体管的控制节点的控制电路。 控制电路可以被配置为在像素电路的检测阶段期间选择性地向控制节点施加用于偏置第一和第二晶体管的控制节点的栅极偏置电压，和/或用于复位由像素电路存储的电压的复位电压 电容器。
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239.发明授权公开(公告)号：US08822332B2
公开(公告)日：2014-09-02
申请号：US13871884
申请日：2013-04-26
Inventor： Heimanu Niebojewski , Yves Morand , Cyrille Le Royer , Fabrice Nemouchi
IPC: H01L21/311 , H01L21/28 , H01L29/66 , H01L21/768
CPC classification number: H01L29/66477 , H01L21/28247 , H01L21/76897 , H01L21/823425 , H01L21/823443 , H01L21/823475 , H01L21/84 , H01L29/66545 , H01L29/66606
Abstract: A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.
Abstract translation: 一种用于在MOS晶体管上形成栅极，源极和漏极接触的方法，其具有包括被金属栅极硅化物覆盖的多晶硅的绝缘栅极，该栅极由至少一个由第一绝缘材料制成的隔离物包围，该方法包括以下步骤： a）用第二绝缘材料覆盖结构并使第二绝缘材料平整以到达栅极硅化物; b）氧化栅极，使得栅极硅化物掩埋并覆盖氧化硅; c）选择性地去除所述第二绝缘材料; 以及d）用第一导电材料覆盖所述结构，并且将所述第一导电材料一直调整到所述隔离物顶部的较低水平。
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公开(公告)号：US20140235186A1
公开(公告)日：2014-08-21
申请号：US14177358
申请日：2014-02-11
Inventor： Didier Belot , Yann Deval , Francois Rivet
IPC: H04B1/00
CPC classification number: H04B1/0021 , H04B1/0014 , H04B1/406 , H04B2001/0491 , H04L27/2639 , H04L27/2642
Abstract: A method for generating a radio frequency signal, wherein a signal to be transmitted is decomposed into a weighted sum of periodic basic signals of different frequencies.
Abstract translation: 一种用于产生射频信号的方法，其中待传输的信号被分解成不同频率的周期性基本信号的加权和。
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