公开(公告)号：US20070155142A1

公开(公告)日：2007-07-05

申请号：US11326178

申请日：2005-12-30

Applicant: Been-Yih Jin ,  Brian Doyle ,  Robert Chau ,  Jack Kavalieros

Inventor： Been-Yih Jin ,  Brian Doyle ,  Robert Chau ,  Jack Kavalieros

IPC: H01L21/425

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.

Abstract translation: 一种方法，包括在衬底中的源区和漏区之间形成沟道区，所述沟道区包括第一掺杂物分布; 以及在所述沟道区和所述衬底的阱之间形成阻挡层，所述阻挡层包括不同于所述第一掺杂剂分布的第二掺杂剂分布。 一种在基板上包括栅电极的装置; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层，阻挡层包括不同于沟道区的掺杂物分布并且不同于阱的掺杂剂分布的掺杂剂分布。 一种包括包括微处理器的计算设备的系统，所述微处理器包括形成在衬底中的多个晶体管器件，所述多个晶体管器件中的每一个在所述衬底上包括栅电极; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层。

公开(公告)号：US20070152266A1

公开(公告)日：2007-07-05

申请号：US11322795

申请日：2005-12-29

Applicant: Brian Doyle ,  Justin Brask ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Marko Radosavljevic ,  Robert Chau

Inventor： Brian Doyle ,  Justin Brask ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Marko Radosavljevic ,  Robert Chau

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848

Abstract: The fabrication of a tri-gate transistor formed with a replacement gate process is described. A nitride dummy gate, in one embodiment, is used allowing the growth of epitaxial source and drain regions immediately adjacent to the dummy gate. This reduces the external resistance.

Abstract translation: 描述了用替换栅极工艺形成的三栅极晶体管的制造。 在一个实施例中，使用氮化物虚拟栅极，允许生长与伪栅极紧邻的外延源极和漏极区域。 这减少了外部电阻。

公开(公告)号：US20070134878A1

公开(公告)日：2007-06-14

申请号：US11299102

申请日：2005-12-09

Applicant: Justin Brask ,  Jack Kavalieros ,  Brian Doyle ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Brian Doyle ,  Robert Chau

IPC: H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.

Abstract translation: 非平面微电子器件，制造器件的方法以及包括该器件的系统。 所述非平面微电子器件包括：衬底主体，其包括衬底基座和鳍片，所述鳍片限定其顶部区域处的器件部分; 栅极电介质层，其在所述鳍片的两个横向相对的侧壁上以预定高度延伸，所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层，并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极，并进一步在栅介质层上延伸; 隔离元件，其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限，所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

公开(公告)号：US07220635B2

公开(公告)日：2007-05-22

申请号：US10742678

申请日：2003-12-19

Applicant: Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Chris E. Barns ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

Inventor： Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Chris E. Barns ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/31691 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成高k栅极电介质层，并在高k栅极电介质层上形成牺牲层。 在蚀刻牺牲层之后，在牺牲层的相对侧上形成第一和第二间隔物。 在去除牺牲层以产生位于第一和第二间隔物之间​​的沟槽之后，在高k栅介质层上形成金属层。

公开(公告)号：US20070090416A1

公开(公告)日：2007-04-26

申请号：US11238447

申请日：2005-09-28

Applicant: Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Suman Datta ,  Justin Brask ,  Robert Chau

Inventor： Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Suman Datta ,  Justin Brask ,  Robert Chau

IPC: H01L29/76

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

Abstract translation: 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

公开(公告)号：US20070069293A1

公开(公告)日：2007-03-29

申请号：US11238444

申请日：2005-09-28

Applicant: Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Uday Shah ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

Inventor： Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Uday Shah ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823828 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.

Abstract translation: 一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可以在连续的宽度范围内定义。

公开(公告)号：US20070063306A1

公开(公告)日：2007-03-22

申请号：US11234014

申请日：2005-09-22

Applicant: Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Suman Datta ,  Robert Chau

Inventor： Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Suman Datta ,  Robert Chau

IPC: H01L27/095

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/2022 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/785

Abstract: Embodiments of the invention provide a substrate with a surface having different crystal orientations in different areas. Embodiments of the invention provide a substrate with a portion having a crystal orientation and another portion having a crystal orientation. N— and P-type devices may both be formed on the substrate, with each type of device having the proper crystal orientation for optimum performance.

Abstract translation: 本发明的实施例提供一种具有在不同区域中具有不同晶体取向的表面的基底。 本发明的实施方案提供了具有<100>晶体取向的部分和具有<110>晶体取向的另一部分的基底。 可以在衬底上形成N型和P型器件，每种类型的器件具有适当的晶体取向以实现最佳性能。

公开(公告)号：US07192856B2

公开(公告)日：2007-03-20

申请号：US11037860

申请日：2005-01-18

Applicant: Mark Doczy ,  Lawrence D. Wong ,  Valery M. Dubin ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Mark Doczy ,  Lawrence D. Wong ,  Valery M. Dubin ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.

Abstract translation: 互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。 在一个实施例中，图案化栅极结构可以由多晶硅形成。 可以使用催化金属通过表面活化来填充沟槽，然后通过化学沉积种子层，然后从底部向上填充超融合填充物。

公开(公告)号：US20070040227A1

公开(公告)日：2007-02-22

申请号：US11586791

申请日：2006-10-26

Applicant: Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

Inventor： Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

IPC: H01L29/94

CPC classification number: H01L29/4983 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.

Abstract translation: 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可能暴露于还原反应的垂直部分。 作为还原反应的结果，垂直部分可以转化为金属，这增加了现有的栅电极。 在一些实施例中，在一些实施例中，去除垂直电介质部分减少了边缘电容，并且还可以有利地稍微增加向下扩散而不加热。

公开(公告)号：US20070001173A1

公开(公告)日：2007-01-04

申请号：US11158661

申请日：2005-06-21

Applicant: Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert Chau ,  Brian Doyle

Inventor： Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert Chau ,  Brian Doyle

IPC: H01L29/10

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract translation: 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。