Abstract:
A display may have upper and lower display layers. A layer of liquid crystal material may be interposed between the upper and lower display layers. The display layers may have substrates. The display layers may include a color filter layer having an array of color filter elements on a glass substrate and a thin-film transistor layer having a layer of thin-film transistor circuitry on a glass substrate. Dielectric layers within the display layers such as dielectric layers within the thin-film transistor layer may have differing indices of refraction. Reflections and color shifts due to index of refraction discontinuities may be minimized by interposing graded index dielectric layers between adjacent layers with different indices. The graded index layers may be formed from structures with a continuously varying index of refraction or structures with a step-wise varying index of refraction.
Abstract:
An electronic device may include a display. The display may be formed by an array of light-emitting diodes mounted to the surface of a substrate. The light-emitting diodes may be inorganic light-emitting diodes formed from separate crystalline semiconductor structures. An array of pixel control circuits may be used to control light emission from the light-emitting diodes. Each pixel control circuit may be used to supply drive signals to a respective set of the light-emitting diodes. The pixel control circuits may each have a silicon integrated circuit that includes transistors such as emission enable transistors and drive transistors for supplying the drive signals and may each have thin-film semiconducting oxide transistors that are coupled to the integrated circuit and that serve as switching transistors.
Abstract:
A display may have a thin-film transistor layer formed from a layer of thin-film, transistor circuitry on a substrate. The thin-film transistor layer may overlap a color filter layer. A portion of the thin-film transistor layer may extend past the color filter layer to for a ledge region. Components such as a flexible printed circuit and a display driver integrated circuit may be mounted to the thin-film transistor layer in the ledge region. The components may have alignment marks. The thin-film transistor layer may have a black masking layer that is patterned to form openings for display pixels. In a border area of the display that overlaps the ledge region, the thin-film transistor layer may have alignment mark viewing windows. Alignment marks formed from black masking material in the windows may be aligned with respective alignment marks on the components.
Abstract:
A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack. The TFT stack includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes removing the first photoresist layer, and depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area. The method further includes doping the second portion of the doped semiconductor layer with a third doping dose, the first dose being higher than the second dose and the third dose.
Abstract:
A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.
Abstract:
An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode with an anode and cathode. The anodes may be formed from a patterned layer of metal. Thin-film transistor circuitry in the pixels may include transistors such as drive transistors and switching transistors. Data lines may supply data signals to the pixels and horizontal control lines may supply control signals to the gates of the transistors. A switching transistor may be coupled between a voltage initialization line and each anode. The voltage initialization lines and capacitor structures in the thin-film transistor circuitry may be formed using a layer of metal that is different than the layer of metal that forms the anodes.
Abstract:
An organic light-emitting diode display may have an array of pixel circuits. Each pixel circuit may contain an organic light-emitting diode that emits light, a drive transistor that controls current flow through the diode, and additional transistors such as switching transistors for loading data into the pixel circuit and emission transistors for enabling and disabling current flow through the drive transistor and diode. Gate driver circuitry may produce emission control signals that control the emission transistors. Display driver circuitry may generate a start signal with a digitally controlled pulse width. The start signal may be applied to shift register circuitry in the gate driver circuitry. The pulse width of the start signal may be adjusted to adjust the luminance of the display.
Abstract:
A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.
Abstract:
Devices and methods for increasing the aperture ratio and providing more precise gray level control to pixels in an active matrix organic light emitting diode (AMOLED) display are provided. By way of example, one embodiment includes disposing a gate insulator between a gate of a driving thin-film transistor and a gate of a circuit thin-film transistor. The improved structure of the display facilitates a higher voltage range for controlling the gray level of the pixels, and may increase the aperture ratio of the pixels.
Abstract:
A display may have an array of pixels. Each pixel may have a light-emitting diode that emits light under control of a drive transistor. The organic light-emitting diodes may have a common cathode layer, a common electron layer, individual red, green, and blue emissive layers, a common hole layer, and individual anodes. The hole layer may have a hole injection layer stacked with a hole transport layer. Pixel circuits for controlling the diodes may be formed from a layer of thin-film transistor circuitry on a substrate. A planarization layer may cover the thin-film transistor layer. Lateral leakage current between adjacent diodes can be blocked by shorting the common hole layer to a metal line such as a bias electrode that is separate from the anodes. The metal line may be laterally interposed between adjacent pixels and may be formed on the planarization layer or embedded within the planarization layer.